Errors 
チュートリアル 754
Selecting the Right Series Voltage Reference for AbsoluteAccuracy VoltageOutput DAC Designs
要約: This article provides an in depth analysis, procedure, and selection tables for selecting the optimum series voltage reference for voltage output DACs. It covers all of the important parameters such as: input supply voltage, reference output voltage, initial accuracy, line and load regulation, stability, and noise. In addition four common design examples are given.
When designing a system that includes a digitaltoanalogconverter (DAC) and an external voltage reference, the voltagereferencespecifications are as important as the specifications of the DAC itself.This article explores some of the issues involved with selecting external,threeterminal series voltage references for voltageoutput DACs. Examplesof DAC system designs are used to illustrate the various tradeoffs whenoptimizing for cost, accuracy, or power.
The MAX6006MAX6009 twoterminal shuntreference family is worth considering for ultralowpower applications, as they can generate 1.25V, 2.048V, 2.5V, or 3V with an operating current of only 1µA. Maxim also offers a family of lowcost, industrystandard LM4040 shunt references.
Zenerbased references receive light treatment primarily because of their high inputvoltage requirement (which limits their applicability in systems with lower supply voltages). In spite of this narrowing of focus, many topics covered in this article are applicable to other reference types. For example, the referencevoltage change on a shunt reference caused by varying bias currents is analogous to the load regulation of a series reference, and the effect on the DAC performance can be analyzed in a similar manner.
Figure 1 depicts the connection between a threeterminal, series voltage reference (the MAX6325) and a DAC (the MAX5170) for a typical design. In this case, an external capacitor is shown between the reference and the DAC, but it can usually be eliminated if space is limited and if the DAC does not have rapid power supply or output transient switching. The figure also shows a powersupply filtering input capacitor and a broadband noisereduction capacitor, but both of these capacitors are also optional. Finally, the MAX6325 voltage reference has a TRIM pin that allows the end user to optionally trim out the initial error with an external potentiometer.
Figure 1. Interfacing a threeterminal series voltage reference and a DAC.
Input Supply Voltage: Powersupply input voltage to the reference. Limited on the upper end by the silicon process used for the reference and on the bottom end by the reference output and dropout voltages:
Initial Accuracy: Accuracy is a slight misnomer, as it actually represents the initial outputvoltage error. Specified in % or mV at 25°C. Some fixedvoltage and any adjustable references can be trimmed to improve accuracy.
Reference Output Current: The available load current that the voltage reference can source to the DAC reference input. All of the references covered in this article can also sink current, but not as well.
ReferenceLoad Regulation: Incremental change in reference output voltage for a DC change in reference output current. Specified in µV/µA or equivalently mV/mA, mV (over the entire outputcurrent range), ppm/mA, or %/mA.
InputLine Regulation: Incremental change in reference output voltage for a DC change in input supply voltage. Specified in µV/V.
OutputVoltage Temperature Coefficient (Tempco): Change in reference output voltage for a given change in temperature. Specified in ppm/°C. Maxim uses the box method, where the maximum reference output fractional voltage change is divided by the maximum operatingtemperature range:
Output Noise Voltage: Voltage noise at the reference output. The 1/f component is specified in µVpp over a 0.1Hz to 10Hz bandwidth, and the wideband noise is usually specified in µV_{RMS} over a 10Hz to 10kHz bandwidth.
CapacitiveLoad Stability Range: Range of capacitive loads (includes usersupplied capacitors, the capacitance presented by the load, and stray capacitance) that the reference can tolerate at its output. External capacitors are needed only to limit large loads or supply transients, and can be eliminated in many designs to save board space. A few references have pins where a compensation capacitor (the MAX872) or a noisereduction capacitor (the MAX6325) can be added to improve performance.
All of the Maxim voltageoutput DACs considered in this article use an inverted R2R architecture. From the referencevoltage standpoint, the main characteristic of this DAC architecture is the varying DAC reference input resistance versus DAC code. Care must be taken to ensure that the voltage reference can source enough current at the DAC's minimum reference input resistance and has sufficient load regulation as the DAC codes change. A 4bit example, along with its normalized reference input current, is shown in Figure 2. Note that the reference current at DAC code 0 is not shown in the plot, as all of the switches connected to the reference are open and virtually no reference current flows. Two other DAC specifications important to voltagereference selection are referenceinputvoltage range and DAC output gain.
Figure 2. Inverted R2R architecture and referenceinputcurrent variation (4bit).
Output error is often specified as a onesided value (in LSBs at the DAC resolution), but it actually implies a doublesided error (Figure 3). For example, a 12bit DAC with a 4.096V output range has an ideal LSB step size of 4.096V/4096 = 1mV. If the specified output error in this case is 4LSBs at 12bit resolution, this means the DAC output at any code could be ±4LSBs (or ±4mV) from the ideal value. We define accuracy in terms of how many actual bits we have at our disposal to reach a desired output voltage with at most 1LSB of error:
Figure 3. DAC transfer function and output error (zero offset assumed).
There are several sources that contribute to output error, but some (such as DAC offset) are ignored because they are not relevant to the referencevoltage selection process. Voltagereference error sources that are considered include initial error, tempco, temperature hysteresis, longterm stability, load and line regulation, and output noise. DAC error sources include INL, gain error, gainerror tempco, and output noise.
Although the target error applies over the entire DAC code range, most of the error sources mentioned above cause an effective gainerror variation that is largest near the fullscale (highest DAC codes) of the transfer function (Figure 3). Gain errors are reduced with decreasing DAC code value; these errors are halved at midscale, and they virtually disappear near code zero, where offset error dominates. Error sources that do not exclusively affect the gain error and apply equally over most of the DAC code range include DAC INL and output noise.
INL is typically defined using one of two methods: absolute linearity or endpoint linearity. Absolute linearity compares the DAC linearity to the ideal transferfunction linearity. Endpoint linearity uses the two measured end points to define the linearity (a straight line is drawn between these points), and all other points are compared to this line. In either case, INL should be included in the error analysis. In the latter case, the DAC INL error is zero at the end points, but can be present at DAC code words just inside these values. As an example, for a 12bit DAC with INL defined between the end points of 0V and 4.095V (fullscale), the INL specification applies to DAC codes near 0 and 4095. For maximum error calculations, it is reasonable to add the DAC's INL and noiseinduced output errors to the previously mentioned gain errors that are most severe near code 4095.
Table 1. Requirements for DAC Design Examples
Table 2. VoltageRelated Parameters for DAC Design Examples
*Reference voltage and DAC gain chosen for each design example
*This limit applies to all DACs mentioned in this article.
Figure 4. DesignB reference options: (a) 2.5V (chosen), (b) 2.048V, (c) 1.25V.
Approximate dropout voltages were calculated for each of the design examples (Table 2). All of these voltages are well above the 200mV (or lower) dropout voltages typical of Maxim's voltage references. Because the upper reference input voltage of most Maxim DACs is limited to VDD  1.4V, dropout voltages can normally be ignored with these designs if the DAC and the voltage reference use the same positive supply rail. The dropout voltages are approximate, because they were calculated without any error terms such as initial accuracy, but these errors are small compared to typical dropout voltages and can be ignored.
Table 3. Initial DeviceSelection Considerations
*Initial reference selection for each design example
The MAX6002 could be used if the accuracy requirement is loosened further or if some type of calibration scheme is implemented, whereas the more expensive MAX6125 could probably meet the requirements without compromise. Assuming the accuracy requirement is rigid, this example illustrates a key tradeoff in reference selection for DAC designs: initial component cost (the MAX6125) versus cost of calibration (the MAX6002).
Further study of the Maxim voltagereference selection table reveals a better option for Design A. If we arbitrarily allocate half of the total error (8LSB at 10 bits ~ 0.8%) to the initial accuracy and half to the tempco (0.8% = 8000ppm/70°C = 114ppm/°C), the MAX6102 ($0.55/2500pcs, 0.4% initial accuracy, 75ppm/°C) surfaces as the best choice. The MAX6102 can source 5mA of current to the load, so it is able to drive the MAX5304 DAC's reference input (2.5V/18 kΩ ~ 140µA max). If the MAX6102 is ruled out when the other error terms are analyzed, the MAX6125 can be reconsidered as a backup alternative.
A 12V supply is conveniently present in the DesignB example, allowing the use of the MAX6325, which needs an input voltage of at least 8V. If 8V (or higher) is not available in the system, the MAX6166 (A grade) or MAX6192 (A grade) bandgapbased references could be considered, but a slight relaxation of the system specifications would be required.
After reviewing the initial specifications, it's clear that either device is probably acceptable. However, the MAX6162 is the first choice due to its higher output current. If further analysis shows the MAX6162 to be marginally unacceptable, the MAX6191 could be considered because it has slightly better loadregulation, temperaturehysteresis, and longtermstability specifications.
The MAX6190 price (C grade is $1.45/1000pcs) is in the same range as the MAX6012 price (B grade is $1.35/2500pcs). Either part will probably work in the application. However, the Agrade MAX6012 is especially attractive, because it is available in a SOT233 package, which is ideal for a small, batterypowered, portable instrument.
A quick check of the Agrade MAX6012 reveals the tempcorelated error to be 600ppm (30°C × 20ppm/°C). The initial error of 3200ppm (0.32%) also needs to be considered, as there is no trimming planned for this design. The sum of these two errors is 3800ppm out of the possible 3906ppm design limit. With this marginal situation, it's likely that some of the other specifications considered in the next section (Step 3), such as load regulation, temperature hysteresis, and even line regulation (because of the varying battery voltage), will put us beyond 3906ppm. Because the MAX6012 is probably insufficient, we will forego the SOT233 package and choose the Agrade MAX6190 as a starting point, as its initial error of 1600ppm and 5ppm/°C leave enough room for the other error terms. Reference output current is not a concern for this design, because the MAX6190 can supply 500µA (>>69µA design requirement).
Table 4. Important Specifications for Final Analysis
Each example is analyzed, focusing on the specifications that apply to that particular design. The results of this analysis, along with the results of the previous section, are summarized in an error budget in Table 5.
It is most convenient to do the errorbudget accounting in ppm, although this could be done equivalently in other units such as %, mV, or LSBs. It's important to apply the proper scaling and to use the proper normalization factor to get the correct error values. Reference error terms can be equivalently calculated relative to the reference voltage or the DAC output voltage. For example, if we assume a reference error of 2.5mV (noise, drift, etc.) and a reference voltage of 2.5V, we get the following:
To calculate the variation in reference voltage caused by load regulation, we need to know the worstcase range of currents that the voltage reference supplies to the DAC's reference input. In Step 2, we determined the maximum DAC reference current that the MAX6102 would have to drive: 140µA. The minimum current is close to 0, as the MAX5304 reference input is effectively an open circuit (several GΩ input impedance) when the DAC code value is 0. This means the total outputcurrent variation that the MAX6102 sees is 140µA, and this value should be used for the loadregulation calculation:
In general, it is best to be conservative and use the maximum output current directly for the loadregulation calculation. An exception may be if you're trying to extract the last bit of accuracy from a design and both the maximum and minimum DAC reference input resistance values are well specified. This approach results in a smaller loadregulation error because of the smaller ΔI_{REF}.
Because the power supply is specified as varying for this example, we need to consider the effects of input line regulation on the MAX6102 reference. The powersupply range is specified as 4.5V to 5.5V. From this, a conservative referencevoltage lineregulation calculation is possible:
The final voltagereferencerelated error term to consider is the effect of reference outputnoise voltage. Conveniently, Design A has a signal bandwidth (10Hz to 10kHz) that corresponds to the exact MAX6102 noise voltage bandwidth, so the widebandnoisevoltage specification of 30µV_{RMS} is used directly (that is, bandwidth scaling is not required). Comparing the load and lineregulation values (126µV and 300µV, respectively), we can see that noise is not a major contributor in this design. Using crude approximations to get numbers for the error analysis, we can assume an effective peak noise value of ~42µV (30µV ×√2), which corresponds to 17ppm (10^{6} × 42µV/2.5V) with the DAC gain of 1. We are trying purposefully to keep the noise calculations simple here; a more detailed analysis can be performed if the relative error of the noise is larger or if the design is marginal. Remember that noise is specified as a typical value when judging design margin.
We will now review the relevant MAX5304 DAC specifications that impact accuracy at or near the upper end of the code range. The DAC INL value of ±4LSB (at 10 bits) is used directly. Treating it as a singlesided quantity, as with the other error terms in our analysis, we arrive at a value of 3906ppm (10^{6} × 4/1024). Similarly, the DAC gain error is specified as ±2LSB and results in an error of 1953ppm (10^{6} × 2/1024). The final MAX5304 DAC specification to be considered is gainerror tempco, which gives us a typical error of 70ppm (70°C × 1ppm/°C). The DAC output noise is not specified for the MAX5304, so it is ignored, most likely without adverse consequences in this 6bitaccurate system.
When all of the error sources are added together, we obtain a worstcase error of 15596ppm, which just barely meets our targeterror specification of 15625ppm. When confronted with this marginal situation, we can rationalize that we will probably never see an error of this magnitude, because it assumes worstcase conditions for most parameters. The root sum square (RSS) approach gives an error of 7917ppm, which is valid if the errors are uncorrelated. Some error sources may be correlated, so the truth probably lies somewhere between these two numbers. But regardless of the approach, the DesignA requirements have been met.
Applying the same assumptions that were used in Design A, we find Design B's reference output current variation to be 140µA (coincidentally, the same number as in Design A). This leads to the following loadregulationerror calculation:
Because the bandwidth for Design B is specified as DC to 1kHz, we need to consider both the 1.5µVpp lowfrequency (1/f) noise and the 2.8µV_{RMS} broadband noise specified from 0.1Hz to 10Hz and 10Hz to 1kHz, respectively. Using the same crude RMS to peak approximation as Design A, and adding the two peak noise terms together, we get a total noise estimate of 2ppm at the reference output ([[0.75µV + 2.8µV_{RMS} × √2]/2.5V] × 10^{6}). Notice that this is the same value we would obtain if we calculated it at the DAC output, because the equation would be multiplied by 1.638/1.638 to rescale everything to 4.096V. It's worth mentioning that the peaknoisesum method used here is fairly conservative, yet the total error contribution is still relatively small. An RSS approach is probably more accurate, because the two noise sources are most likely uncorrelated, but this smaller value would be even more "in the noise" (pun intended) compared to the peakvalue approach.
All that remains for the DesignB analysis is to include the DAC error terms. The INL for the Agrade MAX5170 DAC is specified as ±1LSB, which is 61ppm and exactly half of our 122ppm error budget of ±2LSB at 14 bits. The DAC gain error is specified as ±8LSB worstcase, but this error is removed completely by the gain calibration mentioned earlier. The calibration works as follows: The DAC is set to a digital code where the ideal output voltage is known (for example, decimal DAC code 16380 should produce precisely 4.095V at the output). The reference voltage is then trimmed until the DAC output voltage is at this exact value, even if the reference voltage itself is not 2.500V. The MAX5170 DAC does not list a gain tempco, although the gain error is specified over the operatingtemperature range. Because the gain error is calibrated out at only one temperature, Design B should be tested to ensure that the gain does not drift excessively over temperature. The final consideration is the MAX5170 DAC output noise, whose typical peak noise is roughly estimated as 1ppm ([10^{6} × √(1000Hz × π/2) × 80nV_{RMS}/√Hz × √2]/4.096V).
In the end, the final worstcase accuracy is 184ppm (~ ±3LSB at 14 bits), which doesn't quite meet our accuracy target of 122ppm, whereas the RSS accuracy is acceptable at 100ppm. Based on these numbers, we consider the design a success, because it has illustrated the important points and is close to the target accuracy with several conservative assumptions. In a realworld application, this design could be accepted as is, or the accuracy requirements could be loosened slightly. Alternatively, a more expensive reference could be used if this design were not acceptable.
The digital gain calibration is best demonstrated with an example: Assume the DAC output voltage needs to be at the fullscale value of 4.000V, but the ideal decimal DAC code of 4000 results in a measured output of only 3.997V due to various errors in the system. Using digital calibration, a correction value is added to the DAC code to produce the desired result. In this example, when the DAC output voltage of 4.000V is required, a corrected DAC code of 4003 is used instead of 4000. This gain calibration is scaled linearly across the DAC codes, so it has little effect at the lower codes and more impact on the upper codes.
The digital gain calibration accuracy is limited by the 12bit resolution of the DAC, so the best we can hope for is ~ ±1mV or 244ppm (10^{6} × 1mV/4.096V) of error after the calibration has been applied. Note that the accuracy is calculated on a 4.096V scale in this example to maintain consistency, but it could be calculated relative to the +4.000V output range if required by the application, and the error would be slightly higher.
If the required output range in this example were 4.096V, there are other options that could be used to always bias the uncalibrated DAC output voltage above 4.096V, so that the digital gain calibration scheme described in this example could be employed. Such options include the following:
We find Design C's worstcase reference output current variation to be 293µA (2.5V/[14kΩ14kΩ], remember there are two DACs driven by the reference), which is used directly in the loadregulation calculation:
Because referenceload regulation is proportional to the reference output voltage, it can be calculated at either the voltage reference (264µV/2.048V) or the DAC output ((2 × 264µV)/(2 × 2.048V)).
The power supply is constant in this application, so the line regulation is assumed to be 0ppm. With the bandwidth for Design C specified as 0.1Hz to 10Hz, we use half of the 22µVpp lowfrequency (1/f) noise specification (peak value) to arrive at a noise contribution of 5ppm at the reference output (10^{6} × (22µV/2)/2.048V)). As mentioned previously, we get the same 5ppm answer if the calculation is referred to the DAC output, because the equation is just multiplied by 2.0/2.0.
Moving on to the MAX5154 DAC error terms, the Agrade INL is ±0.5LSB, which is 122ppm on the 12bit scale. The DAC gain error is ±3LSB(244ppm), but it is ignored because it was already accounted for in the digital reference/DAC gain calibration mentioned earlier in this step and we don't want to count it twice. The MAX5154 gainerror tempco has a typical value of 4ppm/°C, which gives us a total of 500ppm (125°C × 4ppm/°C). The DAC output noise is not specified for the MAX5154, so it is ignored. We recognize that this could present a problem, but our experience with Design B indicates that DAC noise is usually a relatively small contributor to the total error. Measurements can be performed to confirm this assumption.
The worstcase error for Design C is calculated as 1865ppm, and the RSS error is 874ppm. With a targeterror specification of 977ppm, the current design is marginally acceptable at best, especially given that some typical values were used and the DAC output noise was not considered. The details of Design C will not be rehashed here, because the important points have already been covered. However, some options for improvement are as follows:
The loadregulation error is again calculated from the assumed worstcase MAX5176 DAC reference input current of 69µA:
The power supply varies between 2.7V and 3.6V in this design, so the MAX6190 lineregulation specification of 80µV/V (max) must be included in the analysis:
As with Design C, the bandwidth for Design D is specified as 0.1Hz to 10Hz, so we use half of the 25µVpp lowfrequency (1/f) noise specification to arrive at a peak noise contribution of 10ppm at the reference output (10^{6} × [12.5µV/1.25V]). We expect the same 10ppmreferenceinduced noise term at the DAC output, because the reference voltage and noise see the same DAC gain.
Focusing now on the MAX5176 DAC error terms, the Agrade INL is ±2LSB, which is 488ppm on the 12bit scale. The DAC worstcase gain error of +/8LSB with a 5kΩ load translates to 1953ppm at 12 bits. Like the MAX5170 in Design B, the MAX5176 does not specify a gainerror tempco. This is not a concern in Design D, because it is not a lowdrift design calibrated at one temperature and the maximum DAC gain error is specified over the entire operatingtemperature range. The final consideration is the MAX5176's DAC output noise, whose estimated typical peak value is assumed to be negligible ([10^{6} × (√10Hz × π/2) × 80nV_{RMS}/√Hz × √2]/2.048V) ~ = 0.22ppm).
As with Designs B and C, the worstcase error of 4462ppm exceeds the 3906ppm target error, whereas the 2580ppm RSS error is well below the target. Based on these numbers, Design D is considered to be successful, because it comfortably meets the requirements from an RSS standpoint and has demonstrated the important design concepts. If further improvement is desired, alternative DACs should be considered first, because the MAX6190 is the best lowpower voltage reference available with an output below 1.3V (caused by the VDD  1.4V limitation on DAC reference inputs) and such low quiescent current (35µA).
Step 1. Voltage Ranges and ReferenceVoltage Determination: The powersupply voltage and the DAC outputvoltage range were used to determine viable referencevoltage and DAC gain options.
Step 2. Initial VoltageReference DeviceSelection Criteria: Candidate voltage references were considered, focusing on reference voltage (determined in Step 1), initial accuracy, tempco, and reference output current. From these candidates, an initial device was selected.
Step 3. Final Specification Review and ErrorBudget Analysis: The selected voltagereference and DAC candidates were evaluated using an errorbudget approach to see if they met the design's overall accuracy requirements. To meet the design goals, iteration between Steps 2 and 3 may be required.
When following the design procedure described above, it's convenient to do the error analysis in ppm and to understand how it relates to other systemaccuracy and error measures (Table 6).
Table 6. Accuracy and Error Ranges
The following tables show existing Maxim threeterminal, series voltage references, along with the specifications used in the design procedure. Specifications that contribute to error are expressed in ppm to ease computations and to allow an applestoapples comparison between voltage references. Voltage references of 3V and below (1.2V, 1.25V, 2.048V, 2.5V, and 3.0V) are shown in Table 7, and those above 3V (4.096V, 4.5V, 5V, 10V) are included with the adjustable references in Table 8. For convenience, the devices in both tables are grouped together by reference voltage and listed roughly in order of increasing price.
Table 7. Maxim Series Voltage References and Key Specifications (VREF <= 3.0V)
LF = Low frequency
HF = High frequency
N/S = Not specified
Table 8. Maxim Series Voltage References and Key Specifications (VREF > 3.0V and Adj)
LF = Low frequency
HF = High frequency
N/S = Not specified
Some voltage references are available as a family of parts with different output reference voltages. It's important to note that, within a given family, some specifications in the data sheet can get worse for devices with increasing output voltage. However, when these specifications are viewed relative to the reference voltage, they can remain constant or even improve with increasing voltage. One example is output noise voltage, which generally increases with output voltage because of the higher internal reference gain needed to amplify the ~1.25V bandgap voltage. Although the noise voltage is higher, the reference voltage is also proportionally higher; thus, relative noise measures, such as the ppm results in the tables above, are roughly constant. Another example is the load and lineregulation specifications (µV/µA and µV/V, respectively), which usually worsen in absolute terms with increasing output voltage. When viewed relative to the reference voltage (in ppm/µA and ppm/V), these specifications normally remain flat or actually improve with increasing output voltage.
A Few Words about Voltage References
The main focus of this article is Maxim's threeterminal, series, bandgap voltage references, although buriedzener references are discussed as well. Twoterminal, shunt references are not covered, because threeterminal, series devices are now available at competitive prices and with low quiescent current that is virtually constant versus input voltage.The MAX6006MAX6009 twoterminal shuntreference family is worth considering for ultralowpower applications, as they can generate 1.25V, 2.048V, 2.5V, or 3V with an operating current of only 1µA. Maxim also offers a family of lowcost, industrystandard LM4040 shunt references.
Zenerbased references receive light treatment primarily because of their high inputvoltage requirement (which limits their applicability in systems with lower supply voltages). In spite of this narrowing of focus, many topics covered in this article are applicable to other reference types. For example, the referencevoltage change on a shunt reference caused by varying bias currents is analogous to the load regulation of a series reference, and the effect on the DAC performance can be analyzed in a similar manner.
Figure 1 depicts the connection between a threeterminal, series voltage reference (the MAX6325) and a DAC (the MAX5170) for a typical design. In this case, an external capacitor is shown between the reference and the DAC, but it can usually be eliminated if space is limited and if the DAC does not have rapid power supply or output transient switching. The figure also shows a powersupply filtering input capacitor and a broadband noisereduction capacitor, but both of these capacitors are also optional. Finally, the MAX6325 voltage reference has a TRIM pin that allows the end user to optionally trim out the initial error with an external potentiometer.
Figure 1. Interfacing a threeterminal series voltage reference and a DAC.
Definitions of VoltageReference Specifications
In addition to cost and packaging, several (but not all) specifications will be covered in the discussions on voltagereference selection. These specifications are described in detail in the references listed at the end of the article, so they will be only briefly summarized here. What follow are definitions of the specifications:Input Supply Voltage: Powersupply input voltage to the reference. Limited on the upper end by the silicon process used for the reference and on the bottom end by the reference output and dropout voltages:
V_{IN(MIN)} = V_{REF} + V_{DROPOUT}Reference Output Voltage: Regulated voltage used at the DAC reference input.
Initial Accuracy: Accuracy is a slight misnomer, as it actually represents the initial outputvoltage error. Specified in % or mV at 25°C. Some fixedvoltage and any adjustable references can be trimmed to improve accuracy.
Reference Output Current: The available load current that the voltage reference can source to the DAC reference input. All of the references covered in this article can also sink current, but not as well.
ReferenceLoad Regulation: Incremental change in reference output voltage for a DC change in reference output current. Specified in µV/µA or equivalently mV/mA, mV (over the entire outputcurrent range), ppm/mA, or %/mA.
InputLine Regulation: Incremental change in reference output voltage for a DC change in input supply voltage. Specified in µV/V.
OutputVoltage Temperature Coefficient (Tempco): Change in reference output voltage for a given change in temperature. Specified in ppm/°C. Maxim uses the box method, where the maximum reference output fractional voltage change is divided by the maximum operatingtemperature range:
TCV_{OUT} = 10^{6} × ΔV_{REF(max)}/ V_{REF}  / (T_{MAX}T_{MIN})OutputVoltage Temperature Hysteresis: Change in reference output voltage at +25°C after a temperature cycle (T_{MIN} to T_{MAX}) is applied. Specified as a ratio of voltages expressed in ppm.
TEMPHYST = 10^{6} ×  ΔV_{REF} / V_{REF} , where ΔV_{REF} = V_{REF} before ΔT cycle minus V_{REF} after ΔT cycle.OutputVoltage LongTerm Stability: Change in reference output voltage versus time. Specified in ppm/1000 hours. Cumulative drift beyond a 1000hour interval is not specified, but it is usually much lower than the initial drift, which can itself be improved by PCBlevel burnin.
Output Noise Voltage: Voltage noise at the reference output. The 1/f component is specified in µVpp over a 0.1Hz to 10Hz bandwidth, and the wideband noise is usually specified in µV_{RMS} over a 10Hz to 10kHz bandwidth.
CapacitiveLoad Stability Range: Range of capacitive loads (includes usersupplied capacitors, the capacitance presented by the load, and stray capacitance) that the reference can tolerate at its output. External capacitors are needed only to limit large loads or supply transients, and can be eliminated in many designs to save board space. A few references have pins where a compensation capacitor (the MAX872) or a noisereduction capacitor (the MAX6325) can be added to improve performance.
DAC Considerations
Only bufferedvoltageoutput DACs are discussed, as the key points are easier to illustrate with this architecture. Currentoutput DACs are typically used in a multiplying configuration (MDAC) to provide variable gain, and they usually require external op amps to generate a voltage output.All of the Maxim voltageoutput DACs considered in this article use an inverted R2R architecture. From the referencevoltage standpoint, the main characteristic of this DAC architecture is the varying DAC reference input resistance versus DAC code. Care must be taken to ensure that the voltage reference can source enough current at the DAC's minimum reference input resistance and has sufficient load regulation as the DAC codes change. A 4bit example, along with its normalized reference input current, is shown in Figure 2. Note that the reference current at DAC code 0 is not shown in the plot, as all of the switches connected to the reference are open and virtually no reference current flows. Two other DAC specifications important to voltagereference selection are referenceinputvoltage range and DAC output gain.
Figure 2. Inverted R2R architecture and referenceinputcurrent variation (4bit).
Output Error and Accuracy Definitions
We define output error as the deviation from an ideal output voltage that would be provided by a perfect voltage reference and DAC. It's important to note that we are addressing absolute accuracy in this article, meaning that everything is referenced to an ideal DAC outputvoltage range. For example, a 12bit DAC code 4095 should produce an output of 4.095V with a reference voltage of 4.096V; any deviation from this is an error. This is in contrast to relative accuracy, where the fullscale output is defined more by the application than by an absolute voltage. For example, in a ratiometric system where an ADC and a DAC with equal resolution share a reference, it may not matter (within reason) what the actual reference voltage is, as long as the DACoutput and ADCinput voltages are nearly equivalent for a given digital code.Output error is often specified as a onesided value (in LSBs at the DAC resolution), but it actually implies a doublesided error (Figure 3). For example, a 12bit DAC with a 4.096V output range has an ideal LSB step size of 4.096V/4096 = 1mV. If the specified output error in this case is 4LSBs at 12bit resolution, this means the DAC output at any code could be ±4LSBs (or ±4mV) from the ideal value. We define accuracy in terms of how many actual bits we have at our disposal to reach a desired output voltage with at most 1LSB of error:
Accuracy = DAC Resolution  log_{2}(Error)In our example, we effectively have 10 bits (12  log_{2}(4)) of accuracy, because we can only get to within 1LSB at 10bit resolution (±4mV = ±4/4096 = ±1/1024) of any given ideal DAC output value.
Figure 3. DAC transfer function and output error (zero offset assumed).
There are several sources that contribute to output error, but some (such as DAC offset) are ignored because they are not relevant to the referencevoltage selection process. Voltagereference error sources that are considered include initial error, tempco, temperature hysteresis, longterm stability, load and line regulation, and output noise. DAC error sources include INL, gain error, gainerror tempco, and output noise.
Although the target error applies over the entire DAC code range, most of the error sources mentioned above cause an effective gainerror variation that is largest near the fullscale (highest DAC codes) of the transfer function (Figure 3). Gain errors are reduced with decreasing DAC code value; these errors are halved at midscale, and they virtually disappear near code zero, where offset error dominates. Error sources that do not exclusively affect the gain error and apply equally over most of the DAC code range include DAC INL and output noise.
INL is typically defined using one of two methods: absolute linearity or endpoint linearity. Absolute linearity compares the DAC linearity to the ideal transferfunction linearity. Endpoint linearity uses the two measured end points to define the linearity (a straight line is drawn between these points), and all other points are compared to this line. In either case, INL should be included in the error analysis. In the latter case, the DAC INL error is zero at the end points, but can be present at DAC code words just inside these values. As an example, for a 12bit DAC with INL defined between the end points of 0V and 4.095V (fullscale), the INL specification applies to DAC codes near 0 and 4095. For maximum error calculations, it is reasonable to add the DAC's INL and noiseinduced output errors to the previously mentioned gain errors that are most severe near code 4095.
DAC Design Examples
To illustrate the steps involved with voltagereference selection for DACs, a few design examples were created to cover a range of applications (Table 1). Only 10, 12, and 14bit DAC designs are included in these examples, because they are the most instructive. The design steps are broken into individual sections by design examples (see Design A, Design B, and so forth).Table 1. Requirements for DAC Design Examples





Main Design Objectives





Example Application





DAC





Minimum Reference Input Resistance





Output Voltage





DAC Output





Power Supply

4.5V min 5.5V max 
4.95V min +12V available 
4.75V min 5.25V max 
2.7V min 3.6V max 
Temperature Range





Signal BW





DAC Calibration





Maximum Error Target





Step 1: Voltage Ranges and ReferenceVoltage Determination
The first consideration when selecting a voltage reference for a DAC application is to evaluate the supplyvoltage and the DAC outputvoltage ranges (Table 2). To simplify the design examples described above, DACs have already been chosen, so their output gain is not a variable we will trade off as in a real design.Table 2. VoltageRelated Parameters for DAC Design Examples





Main Design Objectives 




Example Application 




Output Voltage 




Power Supply 
4.5V min 5.5V max 
4.95V min +12V available 
4.75V min 5.25V max 
V_{BATT}) 2.7V min 3.6V max 
Reference Voltage and DAC Gain Options for Desired Output Voltage 




Dropout Voltage 




*Reference voltage and DAC gain chosen for each design example
Design A: Low Cost, Loose Accuracy
For the DesignA example, VDD is 5V and the output range is 02.5V, so a 2.5V reference is used and the MAX5304 force/sense output is set to unity gain (OUT and FB pins shorted). A lower voltage reference could be used with a higher, externally set gain, but we have opted to save the two resistors for this lowcost design.Design B: High Absolute Accuracy and Precision
A 2.5V reference is chosen for the DesignB example, as the MAX5170 gain is fixed at 1.638 and a final outputvoltage range of 04.096V is required. If a lower reference voltage is desired for Design B, a MAX5171 DAC could be used and its output force/sense gain could be set higher than 1.638 with external resistors, as shown in Figure 4. Note that the minimum VDD level is 4.95V, so the highest reference voltage we could use is 4.95V  1.4V = 3.55V, as the DAC reference input is limited to (VDD  1.4V)*.*This limit applies to all DACs mentioned in this article.
Figure 4. DesignB reference options: (a) 2.5V (chosen), (b) 2.048V, (c) 1.25V.
Design C: OneTime Calibrated, Low Drift
In the DesignC example, the MAX5154 has a fixed gain of 2, so a 2.048V reference provides a nominal 4.096V output at fullscale. This voltage must exceed our 4.000V design requirement, so that we can use a gain calibration to scale the voltage down to the 0V to 4V range. This design also has other referencevoltage options if the MAX5156 force/sense DAC is used. Note that the referenceinput upperlimit voltage is 4.75V  1.4V = 3.35V.Design D: Low Voltage, Battery Powered, Moderate Accuracy
The minimum VDD is 2.7V in the DesignD example, so the largest reference voltage that could be used is 2.7V  1.4V = 1.3V. For this example, a 1.25V reference satisfies the 0V to 2.048V output range, as the MAX5176 gain is 1.638. It's important that the worstcase reference voltage, including all error terms, remains below 1.3V, or the specification for the DAC reference input voltage will be exceeded.Approximate dropout voltages were calculated for each of the design examples (Table 2). All of these voltages are well above the 200mV (or lower) dropout voltages typical of Maxim's voltage references. Because the upper reference input voltage of most Maxim DACs is limited to VDD  1.4V, dropout voltages can normally be ignored with these designs if the DAC and the voltage reference use the same positive supply rail. The dropout voltages are approximate, because they were calculated without any error terms such as initial accuracy, but these errors are small compared to typical dropout voltages and can be ignored.
Step 2: Initial VoltageReference DeviceSelection Criteria
There are many factors to consider when selecting the optimum reference for each design. To make the procedure manageable, candidate devices will be identified based on the reference voltage determined above, an estimate of required initial accuracy, an approximated temperature coefficient, and the reference output current needed for the chosen DAC (Table 3). Other factors such as cost, quiescent current, packaging, and a quick glimpse at the remaining specifications will be used to select a specific initial device for each design. The remaining specifications will be analyzed in the following section (Step 3) to determine if the devices satisfy the overall accuracy requirements.Table 3. Initial DeviceSelection Considerations





Main Design Objectives





Example Application





DAC Calibration





Maximum Error Target





Estimated Initial Accuracy (from Step 2)





Estimated Tempco (from Step 2)





Reference Voltage(V_{REF}) (from Step 1)





Minimum Reference Input Resistance from Data Sheet
(R_{MIN})





Maximum Output Current Requirement (V_{REF}/R_{MIN}) 




VoltageReference Candidates (Initial Accuracy,
Tempco, Output Current)

(1%,100ppm/°C, 400µA) MAX6102* (0.4%, 75ppm/°C, 5mA) MAX6125 (1%, 50ppm/°C, 1mA) 
(0.04/0.12%, 2/5ppm/°C,5mA) MAX6325* (0.04%, 1ppm/°C, 15mA) 
(0.1/0.24%, 5/10ppm/°C, 5mA) MAX6191A/B/C (0.1/0.24/0.5%, 5/10/25ppm/°C, 500µA) 
(0.32/0.48%, 20/30ppm/°C, 500µA) MAX6190A*/B/C (0.16/0.32/0.48%, 5/10/25ppm/°C, 500µA) 
*Initial reference selection for each design example
Design A: Low Cost, Loose Accuracy
At first glance, the MAX6002 ($0.39/2500pcs) appears to be an obvious choice for Design A, which requires low cost and fairly loose accuracy. But a further look reveals that the MAX6002 is not a good option. Its combined initial accuracy (1%, which is ~10LSB at 10 bits) and tempco error (70°C × 100ppm/°C = 7000ppm ~ 7LSB at 10 bits) already violate the overall accuracy requirement of Design A (17LSB exceeds the design requirement of 16LSB at 10 bits), even without including the other error terms such as load regulation, noise, and so forth. The MAX6125 also has 1% accuracy, and its 50ppm/°C tempco brings us within the DesignA error limit (~13.5LSB), but its cost ($0.95/1000pcs) is too high for this application.The MAX6002 could be used if the accuracy requirement is loosened further or if some type of calibration scheme is implemented, whereas the more expensive MAX6125 could probably meet the requirements without compromise. Assuming the accuracy requirement is rigid, this example illustrates a key tradeoff in reference selection for DAC designs: initial component cost (the MAX6125) versus cost of calibration (the MAX6002).
Further study of the Maxim voltagereference selection table reveals a better option for Design A. If we arbitrarily allocate half of the total error (8LSB at 10 bits ~ 0.8%) to the initial accuracy and half to the tempco (0.8% = 8000ppm/70°C = 114ppm/°C), the MAX6102 ($0.55/2500pcs, 0.4% initial accuracy, 75ppm/°C) surfaces as the best choice. The MAX6102 can source 5mA of current to the load, so it is able to drive the MAX5304 DAC's reference input (2.5V/18 kΩ ~ 140µA max). If the MAX6102 is ruled out when the other error terms are analyzed, the MAX6125 can be reconsidered as a backup alternative.
Design B: High Absolute Accuracy and Precision
Because Design B has such challenging accuracy requirements, the MAX6225 and MAX6325 buriedzener references are the initial candidates because they have such low tempcos, excellent longterm stability, and low noise. These devices also have very good initial accuracy, but this is a moot specification in the case of Design B, as gain errors caused by the DAC and the voltage reference are calibrated out. The MAX6225 and the MAX6335 source 15mA, so driving the MAX5170 DAC reference input (2.5V/18k ~ 140µA max) is not an issue. The MAX6325 is chosen because it has the only tempco (70°C × 1ppm/°C = 70ppm max) that puts us beneath the overall 122ppm accuracy requirement (2LSB @ 14 bits = 2/2^{14} = 2/16384 = 1.22 × 10^{4} = 122ppm) while leaving margin for the other error sources. If we relax the DesignB accuracy requirements slightly, the MAX6225 Agrade device (2ppm/°C max tempco) would allow us to cut the reference cost by more than half.A 12V supply is conveniently present in the DesignB example, allowing the use of the MAX6325, which needs an input voltage of at least 8V. If 8V (or higher) is not available in the system, the MAX6166 (A grade) or MAX6192 (A grade) bandgapbased references could be considered, but a slight relaxation of the system specifications would be required.
Design C: OneTime Calibrated, Low Drift
The MAX6162 and MAX6191 Agrade devices are considered because of their low tempcos (5ppm/°C max), which are necessary to meet the requirements of Design C:Total Error Budget is 4LSB at 12 bits = 4 / 4096 ×10^{6} = 977ppmNote that the MAX6162 and the MAX6191 both have 2mV (977ppm) initial accuracy, but this is not a concern with the 2.048V reference because the outputvoltage range is only 04.000V and a gain calibration is planned for this design. The MAX6162 (5mA of output current drive) and the MAX6191 (500µA of output current drive) are both capable of driving the 293µA reference input current that results when the two MAX5154 DAC reference pins are tied together (2.048V/[14kΩ14kΩ]); however, the MAX6162 has more margin if additional loads are connected to the reference output. The MAX6162 does have higher quiescent current than the MAX6191 (120µA versus 35µA max), but this is not a deciding factor as Design C is not powerconstrained.
Required Tempco <= 977ppm / (85  (40)) °C = 7.8ppm / °C
Available Error Beyond Tempco = 977ppm  5ppm / °C ×125°C = 352ppm
After reviewing the initial specifications, it's clear that either device is probably acceptable. However, the MAX6162 is the first choice due to its higher output current. If further analysis shows the MAX6162 to be marginally unacceptable, the MAX6191 could be considered because it has slightly better loadregulation, temperaturehysteresis, and longtermstability specifications.
Design D: Low Voltage, Battery Powered, Moderate Accuracy
Following the approaches used in the other examples, the total error for Design D is found to be 3906ppm (10^{6} × 16/4096). Over the narrow 15°C to 45°C temperature range, we can tolerate a tempco of at most 130.2ppm/°C (3906ppm/30°C). Using our rule of thumb from Design A to allocate roughly half of the error budget to the tempco (<65ppm/°C), reasonable, conservative reference choices are the MAX6012 (A and B grades are 20ppm/°C and 30ppm/°C, respectively) and the MAX6190 (A, B, and C grades are 5ppm/°C, 10ppm/°C, and 25ppm/°C, respectively). These parts are considered, because they have a maximum quiescent current of 35µA, which is appropriate for the lowpower needs of Design D.The MAX6190 price (C grade is $1.45/1000pcs) is in the same range as the MAX6012 price (B grade is $1.35/2500pcs). Either part will probably work in the application. However, the Agrade MAX6012 is especially attractive, because it is available in a SOT233 package, which is ideal for a small, batterypowered, portable instrument.
A quick check of the Agrade MAX6012 reveals the tempcorelated error to be 600ppm (30°C × 20ppm/°C). The initial error of 3200ppm (0.32%) also needs to be considered, as there is no trimming planned for this design. The sum of these two errors is 3800ppm out of the possible 3906ppm design limit. With this marginal situation, it's likely that some of the other specifications considered in the next section (Step 3), such as load regulation, temperature hysteresis, and even line regulation (because of the varying battery voltage), will put us beyond 3906ppm. Because the MAX6012 is probably insufficient, we will forego the SOT233 package and choose the Agrade MAX6190 as a starting point, as its initial error of 1600ppm and 5ppm/°C leave enough room for the other error terms. Reference output current is not a concern for this design, because the MAX6190 can supply 500µA (>>69µA design requirement).
Step 3: Final Specification Review and ErrorBudget Analysis
With the preliminary selection of references complete and backup ICs in place, it's now time to verify the remaining specifications, which include referenceload regulation, inputline regulation, outputvoltage temperature hysteresis, outputvoltage longterm stability, and output noise voltage. The key systemlevel and DAC specifications for each design are also needed for the analysis (Table 4).Table 4. Important Specifications for Final Analysis





Main Design Objectives





Example Application





DAC

10bit single 
14bit single 
12bit dual 
12bit single 
DAC Output





Voltage Reference



A grade 
A grade 
Reference Voltage





Reference Initial Accuracy





Selected Reference Tempco (maximum)





ReferenceLoad Regulation 




Temperature Range 




Signal BW 




DAC Calibration 




Max Error Target





Each example is analyzed, focusing on the specifications that apply to that particular design. The results of this analysis, along with the results of the previous section, are summarized in an error budget in Table 5.
It is most convenient to do the errorbudget accounting in ppm, although this could be done equivalently in other units such as %, mV, or LSBs. It's important to apply the proper scaling and to use the proper normalization factor to get the correct error values. Reference error terms can be equivalently calculated relative to the reference voltage or the DAC output voltage. For example, if we assume a reference error of 2.5mV (noise, drift, etc.) and a reference voltage of 2.5V, we get the following:
Reference Output Error = 10^{6} × 2.5mV / 2.5V = 1000ppmIf we assume that the DAC output amplifier has a gain of 2.0, both the error and the reference voltage are scaled, so we get the same result at the DAC output (5V fullscale range):
DAC Output Error = 10^{6} × (2.5mV × 2) / (2.5V × 2) = 1000ppmTable 5. ErrorBudget Analysis





Main Design Objectives





Example Application





Reference Initial Error





Reference/DAC Post Calibration Error





Reference Tempco Error





Reference Temperature Hysteresis





Reference LongTerm Stability





Reference LoadRegulation Error





Reference LineRegulation Error 




Reference Output Noise 




DAC INL 




DAC Gain Error 




DAC Gain TC 




DAC Noise 




WorstCase Error 




Root Sum Square Error 




Target Error 




WorstCase Margin 




Root Sum Square Margin 




Design A: Low Cost, Loose Accuracy
No calibration or trimming is planned for Design A, so the MAX6102 initial error of 4000ppm (or 0.4%) directly becomes part of the budget, as does the 5250ppm due to the voltagereference tempco (70°C × 75ppm/°C). The typical MAX6102 outputvoltage temperaturehysteresis specification is also used directly in the error budget (keeping in mind that this is a typical value if we find ourselves with a design having marginal accuracy). For outputvoltage longterm stability, we assume twice the MAX6102 1000hour specification (2 × 50ppm = 100ppm), which is fairly conservative, as it's usually much better after the first 1000 hours. A conservative estimate here at least partially offsets the typical specification used for temperature hysteresis.To calculate the variation in reference voltage caused by load regulation, we need to know the worstcase range of currents that the voltage reference supplies to the DAC's reference input. In Step 2, we determined the maximum DAC reference current that the MAX6102 would have to drive: 140µA. The minimum current is close to 0, as the MAX5304 reference input is effectively an open circuit (several GΩ input impedance) when the DAC code value is 0. This means the total outputcurrent variation that the MAX6102 sees is 140µA, and this value should be used for the loadregulation calculation:
LoadRegulation Error  = 140µA × 0.9mV / mA = 126µV (max) 
= 10^{6} × 126µV / 2.5V = 50ppm (max) 
In general, it is best to be conservative and use the maximum output current directly for the loadregulation calculation. An exception may be if you're trying to extract the last bit of accuracy from a design and both the maximum and minimum DAC reference input resistance values are well specified. This approach results in a smaller loadregulation error because of the smaller ΔI_{REF}.
Because the power supply is specified as varying for this example, we need to consider the effects of input line regulation on the MAX6102 reference. The powersupply range is specified as 4.5V to 5.5V. From this, a conservative referencevoltage lineregulation calculation is possible:
LineRegulation Error  = (5.5V  4.5V) × 300µV / V = 300µV (max) 
= 10^{6} × 300µV / 2.5V = 120ppm (max) 
The final voltagereferencerelated error term to consider is the effect of reference outputnoise voltage. Conveniently, Design A has a signal bandwidth (10Hz to 10kHz) that corresponds to the exact MAX6102 noise voltage bandwidth, so the widebandnoisevoltage specification of 30µV_{RMS} is used directly (that is, bandwidth scaling is not required). Comparing the load and lineregulation values (126µV and 300µV, respectively), we can see that noise is not a major contributor in this design. Using crude approximations to get numbers for the error analysis, we can assume an effective peak noise value of ~42µV (30µV ×√2), which corresponds to 17ppm (10^{6} × 42µV/2.5V) with the DAC gain of 1. We are trying purposefully to keep the noise calculations simple here; a more detailed analysis can be performed if the relative error of the noise is larger or if the design is marginal. Remember that noise is specified as a typical value when judging design margin.
We will now review the relevant MAX5304 DAC specifications that impact accuracy at or near the upper end of the code range. The DAC INL value of ±4LSB (at 10 bits) is used directly. Treating it as a singlesided quantity, as with the other error terms in our analysis, we arrive at a value of 3906ppm (10^{6} × 4/1024). Similarly, the DAC gain error is specified as ±2LSB and results in an error of 1953ppm (10^{6} × 2/1024). The final MAX5304 DAC specification to be considered is gainerror tempco, which gives us a typical error of 70ppm (70°C × 1ppm/°C). The DAC output noise is not specified for the MAX5304, so it is ignored, most likely without adverse consequences in this 6bitaccurate system.
When all of the error sources are added together, we obtain a worstcase error of 15596ppm, which just barely meets our targeterror specification of 15625ppm. When confronted with this marginal situation, we can rationalize that we will probably never see an error of this magnitude, because it assumes worstcase conditions for most parameters. The root sum square (RSS) approach gives an error of 7917ppm, which is valid if the errors are uncorrelated. Some error sources may be correlated, so the truth probably lies somewhere between these two numbers. But regardless of the approach, the DesignA requirements have been met.
Design B: High Accuracy and Precision
The initial error of the Agrade MAX6225 is 0.04% or 400ppm, which exceeds Design B's entire 122ppm error budget. Because this application has gain calibration, virtually all of this reference initial error can be removed, assuming the calibration equipment has sufficient (~1µV) accuracy and the trim circuit has enough precision. The tempco contribution is calculated as 70ppm (70°C × 1ppm/°C), and the typical temperature hysteresis value of 20ppm is used directly. The longterm stability specification of 30ppm is also used rather than a more conservative number, because the instrument in this application has an initial burnin as well as an annual calibration.Applying the same assumptions that were used in Design A, we find Design B's reference output current variation to be 140µA (coincidentally, the same number as in Design A). This leads to the following loadregulationerror calculation:
LoadRegulation Error = 140µA × 6ppm / mA ~= 1ppm (max)The power supply is specified as being constant in this application, so the line regulation is assumed to be 0ppm. Note that it would be <1ppm even if the power supply weren't constant, as long as it remained within the specified 4.95V to 5.05V range, because the MAX6325 lineregulation specification is 7ppm/V max.
Because the bandwidth for Design B is specified as DC to 1kHz, we need to consider both the 1.5µVpp lowfrequency (1/f) noise and the 2.8µV_{RMS} broadband noise specified from 0.1Hz to 10Hz and 10Hz to 1kHz, respectively. Using the same crude RMS to peak approximation as Design A, and adding the two peak noise terms together, we get a total noise estimate of 2ppm at the reference output ([[0.75µV + 2.8µV_{RMS} × √2]/2.5V] × 10^{6}). Notice that this is the same value we would obtain if we calculated it at the DAC output, because the equation would be multiplied by 1.638/1.638 to rescale everything to 4.096V. It's worth mentioning that the peaknoisesum method used here is fairly conservative, yet the total error contribution is still relatively small. An RSS approach is probably more accurate, because the two noise sources are most likely uncorrelated, but this smaller value would be even more "in the noise" (pun intended) compared to the peakvalue approach.
All that remains for the DesignB analysis is to include the DAC error terms. The INL for the Agrade MAX5170 DAC is specified as ±1LSB, which is 61ppm and exactly half of our 122ppm error budget of ±2LSB at 14 bits. The DAC gain error is specified as ±8LSB worstcase, but this error is removed completely by the gain calibration mentioned earlier. The calibration works as follows: The DAC is set to a digital code where the ideal output voltage is known (for example, decimal DAC code 16380 should produce precisely 4.095V at the output). The reference voltage is then trimmed until the DAC output voltage is at this exact value, even if the reference voltage itself is not 2.500V. The MAX5170 DAC does not list a gain tempco, although the gain error is specified over the operatingtemperature range. Because the gain error is calibrated out at only one temperature, Design B should be tested to ensure that the gain does not drift excessively over temperature. The final consideration is the MAX5170 DAC output noise, whose typical peak noise is roughly estimated as 1ppm ([10^{6} × √(1000Hz × π/2) × 80nV_{RMS}/√Hz × √2]/4.096V).
In the end, the final worstcase accuracy is 184ppm (~ ±3LSB at 14 bits), which doesn't quite meet our accuracy target of 122ppm, whereas the RSS accuracy is acceptable at 100ppm. Based on these numbers, we consider the design a success, because it has illustrated the important points and is close to the target accuracy with several conservative assumptions. In a realworld application, this design could be accepted as is, or the accuracy requirements could be loosened slightly. Alternatively, a more expensive reference could be used if this design were not acceptable.
Design C: OneTime Calibrated, Low Drift
The initial error of the Agrade MAX6162 is 0.1%, which consumes the entire DesignC error budget of 977ppm. However, like Design B, this is (at least partially) calibrated out. Note that the uncalibrated +4.096V MAX5154 DAC fullscale output voltage exceeds the required +4.000V output range, and the DAC has 1mV resolution even though only ±4mV of accuracy is required. Therefore, it is possible to do a "digital calibration" on the DAC input digital codes to remove some of the reference's initial error and the DAC's gain error.The digital gain calibration is best demonstrated with an example: Assume the DAC output voltage needs to be at the fullscale value of 4.000V, but the ideal decimal DAC code of 4000 results in a measured output of only 3.997V due to various errors in the system. Using digital calibration, a correction value is added to the DAC code to produce the desired result. In this example, when the DAC output voltage of 4.000V is required, a corrected DAC code of 4003 is used instead of 4000. This gain calibration is scaled linearly across the DAC codes, so it has little effect at the lower codes and more impact on the upper codes.
The digital gain calibration accuracy is limited by the 12bit resolution of the DAC, so the best we can hope for is ~ ±1mV or 244ppm (10^{6} × 1mV/4.096V) of error after the calibration has been applied. Note that the accuracy is calculated on a 4.096V scale in this example to maintain consistency, but it could be calculated relative to the +4.000V output range if required by the application, and the error would be slightly higher.
If the required output range in this example were 4.096V, there are other options that could be used to always bias the uncalibrated DAC output voltage above 4.096V, so that the digital gain calibration scheme described in this example could be employed. Such options include the following:
 Using an adjustable reference whose output is always above 4.096V when all circuit tolerances are considered
 Using a force/sense DAC with the gain set slightly higher than necessary
 Adding an output buffer with gain
We find Design C's worstcase reference output current variation to be 293µA (2.5V/[14kΩ14kΩ], remember there are two DACs driven by the reference), which is used directly in the loadregulation calculation:
LoadRegulation Error  = 293µA × 0.9mV / mA = 264µV (max) 
= 10^{6} × 264µV / 2.048V = 129ppm (max) 
Because referenceload regulation is proportional to the reference output voltage, it can be calculated at either the voltage reference (264µV/2.048V) or the DAC output ((2 × 264µV)/(2 × 2.048V)).
The power supply is constant in this application, so the line regulation is assumed to be 0ppm. With the bandwidth for Design C specified as 0.1Hz to 10Hz, we use half of the 22µVpp lowfrequency (1/f) noise specification (peak value) to arrive at a noise contribution of 5ppm at the reference output (10^{6} × (22µV/2)/2.048V)). As mentioned previously, we get the same 5ppm answer if the calculation is referred to the DAC output, because the equation is just multiplied by 2.0/2.0.
Moving on to the MAX5154 DAC error terms, the Agrade INL is ±0.5LSB, which is 122ppm on the 12bit scale. The DAC gain error is ±3LSB(244ppm), but it is ignored because it was already accounted for in the digital reference/DAC gain calibration mentioned earlier in this step and we don't want to count it twice. The MAX5154 gainerror tempco has a typical value of 4ppm/°C, which gives us a total of 500ppm (125°C × 4ppm/°C). The DAC output noise is not specified for the MAX5154, so it is ignored. We recognize that this could present a problem, but our experience with Design B indicates that DAC noise is usually a relatively small contributor to the total error. Measurements can be performed to confirm this assumption.
The worstcase error for Design C is calculated as 1865ppm, and the RSS error is 874ppm. With a targeterror specification of 977ppm, the current design is marginally acceptable at best, especially given that some typical values were used and the DAC output noise was not considered. The details of Design C will not be rehashed here, because the important points have already been covered. However, some options for improvement are as follows:
 Use the MAX6191 instead of the MAX6162, because it has better load regulation (0.55µV/µA versus 0.9mV/mA), temperature hysteresis (75ppm versus 80ppm), and longterm stability (50ppm versus 80ppm). The end result would be a 1750ppm worstcase error and an 858ppm RSS error, which is a net change of 115ppm and 16ppm, respectively. This is a slight improvement, but may not be enough.
 Reexamine the overall systemaccuracy specifications to determine if any parameters can be relaxed. The existing design could be the best choice in terms of accuracy versus cost.
 Reduce the temperature range if the entire extended range is not needed. For example, if the range can be reduced from 40°C to +85°C down to 10°C to +75°C, the worstcase error drops to 1505ppm and the RSS error becomes 648ppm. This is because much of the error budget is consumed by the reference tempco (625ppm) and the DAC gain error tempco (500ppm). Although only one of these error terms is below the 977ppm target, the comfort level is increased considerably compared to the original MAX5154/MAX6162 design.
 If an 8V or greater supply is available, consider the MAX6241 4.096V reference and the MAX5156 DAC (the force/sense version of the MAX5154) set to unity gain. This combination is slightly more expensive, but it produces an approximate worstcase error of 956ppm and an RSS error of 576ppm, both of which are under the 977ppm totalerror target.
 Consider other DACs that have typical gain tempcos as low as 1ppm/°C.
Design D: Low Voltage, Battery Powered, Moderate Accuracy
No calibration or trimming is planned for Design D, so the Agrade MAX6190 initial error of 1600ppm (10^{6} × 2mV/1.25V) is used directly in the error budget, along with 150ppm (30°C × 5ppm/°C) for the tempco error. The 75ppm temperature hysteresis is also used directly, but the risk of using this typical specification is at least partially offset by the reduced operatingtemperature range (15°C to 45°C). Once again, the 1000hour longterm stability is doubled to 100ppm as a conservative estimate of the drift, as there is no burnin in this application.The loadregulation error is again calculated from the assumed worstcase MAX5176 DAC reference input current of 69µA:
LoadRegulation Error  = 69µA × 0.5µV / µA = 34.5µV (max) 
= 10^{6} × 34.5µV / 1.25V = 28ppm (max) 
The power supply varies between 2.7V and 3.6V in this design, so the MAX6190 lineregulation specification of 80µV/V (max) must be included in the analysis:
LineRegulation Error  = (3.6V  2.7V) × 80µV / V = 72µV (max) 
= 10^{6} × 72µV / 1.25V = 58ppm (max) 
As with Design C, the bandwidth for Design D is specified as 0.1Hz to 10Hz, so we use half of the 25µVpp lowfrequency (1/f) noise specification to arrive at a peak noise contribution of 10ppm at the reference output (10^{6} × [12.5µV/1.25V]). We expect the same 10ppmreferenceinduced noise term at the DAC output, because the reference voltage and noise see the same DAC gain.
Focusing now on the MAX5176 DAC error terms, the Agrade INL is ±2LSB, which is 488ppm on the 12bit scale. The DAC worstcase gain error of +/8LSB with a 5kΩ load translates to 1953ppm at 12 bits. Like the MAX5170 in Design B, the MAX5176 does not specify a gainerror tempco. This is not a concern in Design D, because it is not a lowdrift design calibrated at one temperature and the maximum DAC gain error is specified over the entire operatingtemperature range. The final consideration is the MAX5176's DAC output noise, whose estimated typical peak value is assumed to be negligible ([10^{6} × (√10Hz × π/2) × 80nV_{RMS}/√Hz × √2]/2.048V) ~ = 0.22ppm).
As with Designs B and C, the worstcase error of 4462ppm exceeds the 3906ppm target error, whereas the 2580ppm RSS error is well below the target. Based on these numbers, Design D is considered to be successful, because it comfortably meets the requirements from an RSS standpoint and has demonstrated the important design concepts. If further improvement is desired, alternative DACs should be considered first, because the MAX6190 is the best lowpower voltage reference available with an output below 1.3V (caused by the VDD  1.4V limitation on DAC reference inputs) and such low quiescent current (35µA).
DAC VoltageReference Design Summary
This article has demonstrated a design procedure for DAC voltagereference selection involving the following steps:Step 1. Voltage Ranges and ReferenceVoltage Determination: The powersupply voltage and the DAC outputvoltage range were used to determine viable referencevoltage and DAC gain options.
Step 2. Initial VoltageReference DeviceSelection Criteria: Candidate voltage references were considered, focusing on reference voltage (determined in Step 1), initial accuracy, tempco, and reference output current. From these candidates, an initial device was selected.
Step 3. Final Specification Review and ErrorBudget Analysis: The selected voltagereference and DAC candidates were evaluated using an errorbudget approach to see if they met the design's overall accuracy requirements. To meet the design goals, iteration between Steps 2 and 3 may be required.
When following the design procedure described above, it's convenient to do the error analysis in ppm and to understand how it relates to other systemaccuracy and error measures (Table 6).
Table 6. Accuracy and Error Ranges






























































































































The following tables show existing Maxim threeterminal, series voltage references, along with the specifications used in the design procedure. Specifications that contribute to error are expressed in ppm to ease computations and to allow an applestoapples comparison between voltage references. Voltage references of 3V and below (1.2V, 1.25V, 2.048V, 2.5V, and 3.0V) are shown in Table 7, and those above 3V (4.096V, 4.5V, 5V, 10V) are included with the adjustable references in Table 8. For convenience, the devices in both tables are grouped together by reference voltage and listed roughly in order of increasing price.
Table 7. Maxim Series Voltage References and Key Specifications (VREF <= 3.0V)
ences 








MAX6120 








MAX6520 








MAX6001 








MAX6101 








MAX6012 








MAX6190 








MAX6061 








MAX6161 








MAX6021 








MAX6191 








MAX6062 








MAX6162 








MAX6002 








MAX6102 








MAX6125 








MAX6025 








MAX6192 








MAX6066 








MAX873 








MAX6166 








MAX872 








MAX6225 








MX580 








MAX6325 








MAX6003 








MAX6103 








MAX6030 








MAX6193 








MAX6063 








MAX6163 








LF = Low frequency
HF = High frequency
N/S = Not specified
Table 8. Maxim Series Voltage References and Key Specifications (VREF > 3.0V and Adj)
ences 








MAX6004 








MAX6104 








MAX6141 








MAX6041 








MAX6198 








MAX6064 








MAX6164 








MAX874 








MAX6241 








MAX6341 








MAX6145 








MAX6045 








MAX6194 








MAX6067 








MAX6167 








MAX6005 








MAX6105 








REF02 








MAX6150 








MAX6050 








MAX6195 








MAX6065 








MAX875 








MAX6165 








MAX6250 








MAX675 








MAX6350 








REF01 








MAX876 








MX581 








MAX674 








MAX6160 








MX584 








LF = Low frequency
HF = High frequency
N/S = Not specified
Some voltage references are available as a family of parts with different output reference voltages. It's important to note that, within a given family, some specifications in the data sheet can get worse for devices with increasing output voltage. However, when these specifications are viewed relative to the reference voltage, they can remain constant or even improve with increasing voltage. One example is output noise voltage, which generally increases with output voltage because of the higher internal reference gain needed to amplify the ~1.25V bandgap voltage. Although the noise voltage is higher, the reference voltage is also proportionally higher; thus, relative noise measures, such as the ppm results in the tables above, are roughly constant. Another example is the load and lineregulation specifications (µV/µA and µV/V, respectively), which usually worsen in absolute terms with increasing output voltage. When viewed relative to the reference voltage (in ppm/µA and ppm/V), these specifications normally remain flat or actually improve with increasing output voltage.
Key Points
These are the key points in this article: The system designer often has multiple referencevoltage and DAC gain choices to satisfy a given DAC outputvoltage range.
 Consider all error sources, not just initial error (which is important in some designs but not critical for others, such as those with gain calibration).
 Reference and DAC tempcos can be major error contributors. Check the actual required operatingtemperature range, because slight reductions can decrease the error contribution from these parameters significantly.
 A common tradeoff is the higher price of a reference with tight initial accuracy versus the trimming cost in product manufacturing.
 Examine the accuracy requirements carefully to make sure they are correct before selecting unnecessary, more expensive components or reworking a design that has marginal performance. It is generally very difficult (and expensive) to achieve a high level of absolute accuracy, especially at 12 bits and above.
 Worstcase or RSS analysis can be used to quantify the error, but it's ultimately up to the designer to determine if a given design is accurate enough.
References
 Pearson, Mark (Maxim), "Carefully Compare Pros and Cons To Correctly Choose An IC Voltage Reference," Electronic Design, December 18, 2000
 Kenyon, Roger (Maxim), "A quick guide to voltage references," EDN, April 13, 2000
 Miller, Perry and Moore, Doug (Texas Instruments), "Precision voltage references," Analog Applications Journal, November 1999
 Productline pages for Voltage References and DA Converters
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