Mathcad Calculates Input Capacitor for Step-Down Buck Regulator
A capacitor is often represented by a series combination of R, L, and C. R is the equivalent series resistance (ESR) and L is the equivalent series inductance (ESL). The term C is equal to the ideal capacitor value.
Figure 1 shows a typical schematic of a synchronous buck power stage and the associated waveforms to be used for the derivations and calculations.
Figure 1. Typical synchronous buck power and waveforms.
Setting up variables and data for example calculation in MathCad:
|Input Voltage||VI := 12||n := 10-9|
|Output Voltage||VO := 3.3||u := 10-6, k := 10³|
|Output Current||IO := 25||m := 10-3|
|High-Side Switch Drop||VHS := 0.227|
|Low-Side Switch Drop||VLS := 0.113|
|Switching Current Rise Time||TRS := 25 × n|
|Switching Current Fall Time||TFS := 25 × n|
|Switching Frequency||FS := 600 × k|
|Duty Cycle||D := (VO + VLS) / (VI - VHS + VLS)||D = 0.287|
|Switch(Q1) On Time||TON := D / FS|
|Switch(Q1) Off Time||TOFF := 1 / FS - TON|
|Converter Efficiency||η := 0.9|
|Input Current||IIN := VO × IO / η × VI||IIN := 7.639|
|Output Inductor Pk-Pk Ripple Current||
IRPL := 0.3 × IO
|Input Capacitor||CIN := 40 × u||(4 x 10uF ceramic of ESR = 10mΩ each and ESL = 2.5nH each)|
|Input Capacitor ESR||ESRCIN := 2.5 × m|
|Input Capacitor ESL||ESLCIN := 0.625 × n|
As seen in Figure 1, the output ripple current through the input capacitor results in voltage across CIN that reflects the values of ESR, ESL, and C. The ESR and ESL cause fast step voltage rise and fall, whereas C has a linear voltage rise and fall due to the fact that the capacitor charges and discharges. At the start of TON, CIN sees a negative step current, which will produce a negative step voltage given by the following equation:
During TON, the capacitor discharges an average current of (IO-IIN), which causes a linear ΔV of:
The total voltage deviation from the start of TON to the end of TON is the summation of the above:
Similarly, but with opposite polarity, at the start of TOFF and during TOFF, the following voltage deviations are calculated:
The peak-to-peak ripple is equal to the higher of the two, which is ΔVOFF~1V. As seen from the above, most of the ripple is caused by ESL and the fast di/dt. Di/dt of 1A/nS is very realistic in today's MHz DC-DC converters. Therefore, to reduce the ripple, more capacitors would need to be placed in parallel. Lower value ceramic capacitors, such as 0.1uF in the 0805 or 1206 package, have half the ESL of the 10uF, or ~1.2nH. Place the 0.1uF as close as possible to the sensitive decoupling points.
Another parameter that needs to be determined is the RMS current through the input capacitor, so that the capacitor IRMS rating is not exceeded. From the ICIN waveform, the RMS current can be approximated (since the peak-to-peak inductor ripple current is usually 20-30% of IO max) to be:
Where D = (VO + VLS) / (VIN + VLS + VHS), and IIN = (VO × IO) / η × VIN
To simplify further, let D = VO/VIN (since V0 >> VLS, and VIN + VLS - VHS ~ VIN), and IIN = VO × IO/VIN (since efficiency η ~ 1), so that the ICINRMS equation above becomes:
The simplified version produces only ~1.4% error, and involves only three known parameters: VI, VO, and IO. VO is fixed, and IO, VI can have a specified range, depending on the application. However, ICINRMS always has a maximum value of IO/2, which happens at VI = 2VO, and decreases the value for VI < 2IO and VI > 2LO. The plot in Figure 2 below illustrates this:
Due to the high di/dt and pulsating current, a ceramic capacitor is chosen, for its low ESR and ESL. A higher ripple current rating is required at high-frequency to contain the switching spikes. Make sure the RMS current rating of the capacitor is well above the maximum operating RMS current. For long-term reliability, choose a capacitor that will exhibit less than a 10°C temperature rise. Most capacitor manufacturers provide plots that show RMS current vs. temperature rise.