Getting Started with ATE
This application note provides a solution for understanding and design of ATE testers with complex functionality by describing major blocks of pin electronics (PE) devices and depicting different tester architectures.
Automated test equipment (ATE) is a testing apparatus designed to perform a single test or sequence of tests on one or multiple devices at a time. Different types of ATE testers include testing of electronics, hardware, and semiconductor devices, which are supported by Maxim's ATE portfolio of highly integrated pin electronics (PE) devices. These PE devices can deliver signals and power with precise voltages and currents. It can also measure the device under test (DUT) electrical characteristics. This application note describes the major blocks of complex PE devices and depicts different tester architectures, thereby easing the design of ATE testers.
Major blocks of PE devices include a driver, comparator, load, parametric measurement unit (PMU), and device power supply (DPS). Timing devices, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), multiplexers, relays, and switches are the supporting blocks for the mentioned major blocks in the tester. Maxim's wide portfolio of products supports both major PE blocks and supporting blocks. The following section details the major blocks of PE devices.
Driver + Comparator + Load (DCL)
Signals driven from the DCL check DUT functionality over various voltage levels and frequencies by incorporating configurable load conditions. Traditionally, AC characteristics of a device are tested with the DCL block of the tester.
Figure 1. Tester block diagram using a DCL.
Tester speed and power consumption are the critical parameters for ATE products. Maxim's PE drivers can operate at high speed without compromising signal fidelity and offer low power consumption, even at higher frequencies. This is achieved by implementing the PE design in an advanced BiCMOS semiconductor fabrication process. For example, the MAX9979 has a high-speed driver that supports a data rate of 1.1Gbps at 1VP-P with a low power dissipation of 1.2W/channel.
The driver is responsible for switching the device at different voltage levels. Voltage levels in any device are either programmable or set through analog inputs. PE ICs with integrated level-setting DACs support programming different voltage levels through a serial interface. PE ICs without integrated DACs set the voltage levels through analog inputs. External DACs, FPGAs, and power supplies are used in addition to the driver block to configure and provide the analog inputs. Peak-to-peak output voltage determines the maximum data rate at which the PE driver can be operated. The maximum data rate of the device is calculated by the rise/fall time at a specific output-voltage swing.
Three-level and four-level drivers are predominant in today's PE market. Four-level drivers can drive very high voltage (typically VHH ~13V) along with the voltage levels supported by three-level drivers. Three-level drivers can switch the voltage levels between a drive-high voltage (VDH), drive-low voltage (VDL), and termination voltage (VDT), which are voltage levels of analog inputs or internal DHV, DLV, and DTV level-setting DACs, respectively. All of the internal DACs can be configured through an SPI interface.
The driver acts like a multiplexer switch between three or four different voltage levels. Multiplexer switching is controlled by the high-speed differential inputs DATA/NDATA and RCV/NRCV, single-ended input ENVHHP, and mode-control bits TMSEL and ENVHHS. Refer to the data sheet for control word bits and digital inputs to switch on the driver, then switch between the voltage levels—DHV, DLV, DTV and VHH—as detailed in Table 1.
Table 1. Driver Control
|X||X||1||0||0||Drive to DLV|
|X||X||1||0||1||Drive to DHV|
|1||0||1||1||X||Drive to DTV|
|X||1||X||1||X||Drive to VHH|
|X||0||0||X||X||Drive to VHH|
As seen in Figure 2, additional features of the driver include cable droop compensation, slew-rate control, driver voltage clamps, and adjustable output impedance. Typically, a driver has an output impedance of 50Ω, though some parts in Maxim's ATE portfolio support adjustable driver output impedance. In drivers with the adjustable impedance feature, the driver has a fixed impedance of 48Ω and a programmable impedance of ±2.5Ω (with 360mΩ resolution), which can be adjusted through serial interface bits. This helps to overcome the tolerance of coaxial cables used from the tester to the DUT. A slew-rate circuit adjusts the rise and fall times of the driver output voltage. The driver buffer slew rate can be controlled through the serial interface.
Figure 2. Driver block diagram showing the driver's additional features.
Driver Cable Droop Compensation
Operating with lossy interconnects degrades the output waveform at the DUT due to the frequency-dependent voltage drop in the transmission line, thus resulting in a highly degraded or unusable signal. Voltage droop can be compensated through the cable droop compensation circuitry. Maxim's PE driver compensation circuit counters this degradation by adding a double time-constant decaying waveform to the nominal output waveform. Figure 3 depicts a comparison between a typical driver and the cable droop compensated driver. To understand more about the performance issues of cables, refer to Maxim's Application Note 4338: Cable-Loss Solutions.
Figure 3. Cable droop compensation in a typical driver vs. a Maxim ATE driver.
Driver Voltage Clamps
The high- and low-voltage clamps limit the voltage at DUT_ and suppress reflections when the channel is configured as a high-impedance receiver. Clamp voltages can be set using the analog inputs/level-setting DACs (CPHV_ and CPLV_). The clamps are enabled only when the driver is in high-impedance mode. For transient suppression, set the clamp voltages to approximately 0.7V outside the minimum and maximum expected DUT output-voltage range. Overvoltage protection then remains active without loading DUT_. Driver clamps are always and only enabled in driver high-impedance mode.
One input of the high-speed comparator is connected internally to the DUT_ node, and the other input is connected to CHV or CLV (internal DACs or external analog inputs). The output of the comparator is the logical result of the input conditions. High-speed comparators can be of two types—window comparator and differential comparator.
Two individual comparators form a window comparator. Window comparator outputs CH and CL are controlled by the DAC voltages CHV and CLV, as shown in Figure 4. Table 2 shows the truth table for the window comparator. From the truth table, an example condition is when the DUT voltage is within the window between the CLV and CHV voltages (VCLV < VDUT < VCHV), then the CL comparator outputs are high and the CH outputs are low.
Table 2. Window Comparator Truth Table
|VDUT < VCHV||VDUT < VCLV||0||0|
|VDUT < VCHV||VDUT > VCLV||0||1|
|VDUT > VCHV||VDUT < VCLV||1||0|
|VDUT > VCHV||VDUT > VCLV||1||1|
Figure 4. Window comparator showing outputs CH and CL.
A differential comparator compares the voltage levels between two DUTs, as well as the DAC voltages (CHV, CLV), and produces the resulting outputs CH and CL. Suppose that the comparator compares the voltage levels between DUT0, DUT1 and level setters CHV and CLV, then Figure 5 shows the operation of the comparators where VDGS is the voltage at the DUT ground sense. Table 3 shows the truth table for the differential comparator.
Table 3. Differential Comparator Truth Table
|VDUT0 - VDUT1 < VCHV - VDGS||VDUT0 - VDUT1 < VCLV - VDGS||0||0|
|VDUT0 - VDUT1 < VCHV - VDGS||VDUT0 - VDUT1 > VCLV - VDGS||0||1|
|VDUT0 - VDUT1 > VCHV - VDGS||VDUT0 - VDUT1 < VCLV - VDGS||1||0|
|VDUT0 - VDUT1 > VCHV - VDGS||VDUT0 - VDUT1 > VCLV - VDGS||1||1|
Figure 5. Differential comparator.
In the process of testing, the devices must test under either loaded or unloaded conditions. The load block helps in functional testing, plus verifying the voltage and current levels at different load conditions. Serial interface bits can be controlled to enable and disable the load in the PE IC. There are two different types of loads in the PE IC—one is a passive load and the other is an active load.
A PE IC with a passive load has two or more resistive load options that connect a "commutation" voltage (VCOM) or, in this case, a termination level to the DUT through selection switches, as shown in Figure 5. Each path connects to the DUT individually by a switch controlled through the serial interface. The loads facilitate fast open/short testing in conjunction with the comparator and pullup of the open-drain DUT outputs.
Load one (L1) is connected to the DUT when switch one (S1) is enabled. Load two (L2) is connected to the DUT when switch two (S2) is enabled. When both S1 and S2 are enabled, then the load connected to the DUT will be L1 and L2 connected in parallel.
Figure 6. Passive load showing load options.
Active load, also known as programmable current load, acts as a load to the DUT during functional testing. The active load is a linearly programmable current source and sink, commutation buffer, and diode bridge, as shown in Figure 7. Analog control inputs or level-setting DACs set the sink/source currents and commutation buffer output voltage.
Source and sink currents are the currents flowing out of and into the PE's DUT pin, respectively. When the commutation buffer output voltage level is less than the DUT voltage, the current flows from the DUT through the diode bridge to the active load programmable sink (or VLDL) current, causing the device under test to source current. When the commutation buffer output voltage level is greater than the DUT voltage, the current flows from the active load programmable source (or VLDH) current through the diode bridge to the DUT, causing the device under test to sink current. VLDH and VLDL DAC voltages are used to vary the amount of source and sink currents, respectively.
Figure 7. Active load showing the current source and sink, commutation buffer, and diode bridge.
Parametric Measurement Unit (PMU)
The PMU forces and measures currents and voltages into the DUT. Ideally, a PMU is used to test the DC characteristics of a DUT. Test system architecture is composed of either a PMU that can be shared with a group of PE ICs or a PMU for each pin of the DUT known as a per-pin PMU (PPMU). PPMU architecture exponentially reduces the test time, as every DUT pin can be tested simultaneously.
Figure 8. Tester block diagram using PMU.
The PMU has different modes of operation based on whether the PMU output pin is forcing current (FI) or voltage (FV) and the PMU measure pin is measuring voltage (MV) or current (MI). Each PMU has voltage clamps to avoid any transient voltages while in FI mode. It also has current clamps to avoid any transient currents while in FV mode. Refer to Maxim Application Note 4343 to understand force voltage/measure voltage (FVMV), force voltage/measure current (FVMI), force current/measure voltage (FIMV), and force current/measure current (FIMI) modes of the PMU.
PMU Switch vs. PMU
PMU switches provide force and sense paths that are internally connected to the DUT node, allowing another external PMU or DC source. These force and sense paths are controlled through the serial interface. The force path drives the current/voltage to the DUT through the external PMU or DC source through relatively low resistance. The sense path provides a higher resistance (zero current) feedback path from the DUT node.
Device Power Supply (DPS)
A DPS in a testing environment provides the supply voltage required for the DUT. The DPS can be operated in both force voltage (FV) and force current (FI) mode. When the DPS is operating in FI mode, programmable voltage clamps ensure that the voltage is within the range of the DUT. A DPS operating in FV mode acts as voltage source when the load current is within the programmable current limits. If the current limits are reached, then the DPS voltage source transitions into a current source/sink.
The DPS has force and sense lines similar to a typical power supply, as well as the capability to read back and measure the voltage and current. Consider a use case measuring supply current (ICC) by varying the supply voltage (VCC). The force and sense lines of the DPS (operated in FV mode) are connected to device supply pin. The force line provides the required voltage level at the output, and the sense line monitors the applied voltage level. The compensation circuit inside the DPS attempts to maintain a constant supply voltage regardless of the resistance between the DPS and the DUT. Supply current (ICC) is measured through a sense resistor that depends on the selected current range, thus providing an adjustable supply voltage (VCC). PMU and DPS are alike, but the DPS has higher current capabilities than the PMU.
Clamps and Current Limit
The DPS has voltage control inputs that allow independent setting of the output voltage. The DPS output features adjustable clamps that limit negative and positive output voltages and currents. The DPS has modes of operation that are similar to the modes of a PMU. In FV mode, the output voltage is proportional to the input voltage, which is determined by the internal register settings. In FI mode, the output current is proportional to the input voltage, and the constant of proportionality depends on the sense resistor that is internal to the DPS.
Programmable voltage clamps are available to limit the output voltage in FI mode. Programmable current limits are available in FV and FI mode at the output. Enabling, disabling, and setting the voltage clamps and current limits are controlled by internal register settings.
Testers can be widely classified as system-on-chip (SoC) testers or memory testers. In SoC testers, each pin can be tested at different voltage/current levels. In memory testers, several drivers are used to send data to the memory address at the DUT, which are commonly input-only pins; testing readback is not usually necessary on these pins. Because of this one-way communication, the comparator block is more often used in SOC testers than in memory testers. Testing time and tester cost are two important considerations when designing tester architectures. Figures 9, 10, and 11 depict some examples of tester architectures.
Figure 9. Tester architecture with driver and comparator.
Figure 10. Tester architecture with DCL and PPMU.
Figure 11. Tester architecture with DCL and shared PMU.
This application note provides a new user with a broad understanding of ATE products and describes key features that Maxim offers in its ATE portfolio. Maxim's ATE products are drivers, comparators, load (DCLs), PMU, and DPS. Different tester architectures are depicted using combinations of these products.