アプリケーションノート 7091

Communication Noise Immunity of 1-Wire


要約: 1-Wire® networks are often deployed in noisy environments. This application note is a study of 1-Wire slave immunity to noise.

Introduction

Electrical noise can disturb the communication of circuits. In 1-Wire® networks, noise can come from reflections, network endpoints, branch points, and from other sources that get coupled into the 1-Wire line. This can cause signal glitching that results in communication errors. 1-Wire slave devices have features that provide a level of immunity to noise. However, 1-Wire devices are parasitically powered devices with no direct power connection. This can make noise analysis challenging as compared to traditional logic circuits with a connected power supply. Determining what margins of noise are acceptable in a harsh environment can assist the design engineer in their analysis and system implementation. This application note presents a method to determine the limits of typical 1-Wire noise immunity. Tests are shown with these limits for 1-Wire slave devices.

Arrangement

Both the 1-Wire master and slave device characteristics must be considered to understand the noise immunity limits. This application note discusses a typical master/slave configuration using the DS2477 and DS28E50 devices as shown in Figure 1. The 1-Wire slave device chosen has performance representative of authenticators (e.g., DS28E36, DS28E38, DS28E39, DS28E83, and DS28E84). The 1-Wire master device chosen has performance representative of modern 1-Wire drivers that have adjustable timing, strong pullup (SPU), and active pullup (APU) for enhanced 1-Wire slave power delivery.

Typical master/slave configuration for authenticatorsFigure 1. Typical master/slave configuration for authenticators.

Standard Noise Margin Calculations

Noise immunity limits are traditionally expressed in terms of noise margin. For devices without hysteresis, the equations for noise margin low (NML) and noise margin high (NMH) are as follows:

NML = VIL – VOL(EQ. 1a)
NMH = VOH – VIH(EQ. 1b)

For devices with hysteresis, the noise margin equations are as follows:

NML = VIH – VOL(EQ. 2a)
NMH = VOH – VIL(EQ. 2b)

In 1-Wire devices, NML is the noise immunity limit from a rising-edge anomaly that does not produce a faulty high-logic reading when in a logic-low state. Conversely, NMH is the noise immunity limit from a falling edge anomaly that does not produce a faulty low-logic reading when in a logic-high state.

Master Examination

The DS2477 master is sensitive to noise only when it samples the 1-Wire line. The parameters that control sampling are the presence-detect sampling time (tMSP) and the read sample time (tMSR). Sampling occurs at one point in time – it is not continuous. The single-point sample provides some time domain filtering. Noise on the 1-Wire line must not exceed the master’s noise margin limits during this time or data could be misread.

The DS2477 has a programmable slew-rate control for falling edges called tF. Excessively fast slew rates can cause ringing that might affect slave sampling of the 1-Wire line. Excessively slow slew rates might not meet timing requirements. The most appropriate setting is usually 150ns in overdrive and 1300ns in standard.

Master Noise Margin

Input logic parameters always come from the master device (e.g., DS2477) when calculating the master noise margins. We assume a typical system with three DS28E50 devices is connected to a DS2477 with VIL1 and VIH1 set to the medium configuration, VCC = 3.3V, and RWPU nominal = 1k. VIH1 is substituted by VTH to represent a typical system. The DS2477 input buffer has no hysteresis in the medium configuration. Refer to the DS2477 data sheet for more information about the medium configuration. The noise margin equations for master NML and master NMH can be rewritten as follows:

Master NML = VIL1 – VOL TYP (ONE SLAVE)(EQ. 3)

Master NMH = VOH – VIH1(EQ. 4a)

or

Master NMH = VOH – VTH(EQ. 4b)

or

Master NMH = (VCC – (IL(THREE SLAVES) × RWPU)) – 0.4 × VCC(EQ. 4c)

Because the master’s 1-Wire pin is an open drain and cannot drive high, VOH is the voltage drop across the pullup resistor due to leakage current.

Table 1. Typical Measured Data over Temperature (VCC = 3.3V)

Temperature DS2477 VOL TYP DS2477 RWPU TYP DS28E50 VOL TYP DS28E50 IL
25°C 0.03V 1136Ω 0.13V 10µA
55°C 0.03V 1119Ω 0.13V 23µA
85°C 0.03V 1102Ω 0.15V 49µA

Table 2. Typical DS2477 Noise Margins over Temperature (VCC = 3.3V)

Temperature Master NML (Equation 3) Master NMH (Equation 4)
25°C (0.4 × 3.3V) – 0.13V =1.190V (3.3V – (3x10µA × 1136)) – 0.4 × 3.3V = 1.946V
55°C (0.4 × 3.3V) – 0.13V = 1.190V (3.3V – (3x23µA × 1119)) – 0.4 × 3.3V = 1.903V
85°C (0.4 × 3.3V) – 0.15V = 1.170V (3.3V – (3x49µA × 1102) – 0.4 × 3.3V = 1.818V

Slave Examination

The DS28E50 and other 1-Wire slaves all have input buffers with hysteresis. The VTL and VTH of the slave are affected by the slave’s parasitic supply voltage, VDD. The internal slave’s VDD moves up and down during 1-Wire communication. Exact VDD levels depend on the 1-Wire data pattern, CEXT of the slave (if present), the current drawn by the slave during communication, and the DS2477 settings for VCC, RWPU, RAPU, tRSTL, tW0L, tW1L, tRL, and tREC. Under typical conditions for the DS28E50, VTL = 0.65 × VPUP and VTH = 0.75 × VPUP. Figure 2 shows an equivalent circuit for a 1-Wire slave device with hysteresis.

1-Wire front-end equivalent circuit with hysteresisFigure 2. 1-Wire front-end equivalent circuit with hysteresis.

1-Wire slaves are sensitive to noise at three different times in the 1-Wire protocol:

  • Idle: When the 1-Wire is idling high, noise that causes IO to go below VTL is interpreted as the start of a time slot or reset, which causes the slave to become out of sync with the master. At this time, the slave is sensitive to noise at any frequency.
  • Slave sampling: The 1-Wire line is sampled during a write time slot. Sampling occurs at one point in time – it is not continuous. The single-point sample provides some time domain filtering. Noise on the 1-Wire line must not exceed the slave’s noise margin limits during this time or data could be misread.
  • Rising edge: At rising edges of the 1-Wire line during time slots, after VTH has been exceeded, noise or a reflection that causes the 1-Wire line to go below VTL is seen as the start of another time slot. This causes the slave to become out of sync with the master. If the 1-Wire line goes below VTL during the rising-edge hold-off (tREH), the initial crossing of VTH is ignored, and the tREH filter is retriggered upon the next crossing of VTH. In standard speed, this effectively filters noise ≥1MHz (1/tREH) on the rising edges. In overdrive speed, there is nominally 100ns of tREH, which is unspecified, so the filter frequency is ≥10MHz. Figure 3 illustrates tREH filtering of a noise glitch (tGL). Case A and case B cause no error, and Case C causes an error.

tREH filteringFigure 3. tREH filtering.

The DS28E50 and other 1-Wire slaves have slew rate control on the falling edge of the presence pulse called tFPD. This reduces ringing during master sampling time, tMSP. In Figure 2, C2 and R2 form a Miller circuit, which performs the slew rate control.

Slave Noise Margin

Input logic parameters always come from the slave device (e.g., DS28E50) when calculating the slave noise margins. We assume a typical system with three DS28E50 devices connected to a DS2477 configured in a medium configuration with RWPU nominal = 1k with a VCC at 3.3V. Refer to the DS2477 data sheet for more information about the medium configuration.

The slave idle and slave sampling cases are covered by the normal noise margin equations for a buffer with hysteresis, which can be rewritten as follows for slave NML and slave NMH:

Slave NML = VTH – VOL (MASTER)(EQ. 5a)

or

Slave NML = 0.75 × VPUP (EFFECTIVE) - VOL (MASTER)(EQ. 5b)

or

Slave NML = 0.75 × (VCC – (IL(THREE SLAVES) × RWPU)) - VOL (MASTER)(EQ. 5c)

Slave NMH = VOH (MASTER) - VTL(EQ. 6a)

or

Slave NMH = VOH (MASTER) - 0.65 × VPUP (EFFECTIVE)(EQ. 6b)

or

Slave NMH = (VCC – (IL(THREE SLAVES) × RWPU)) - 0.65 × (VCC – (IL(THREE SLAVES) × RWPU))(EQ. 6c)

or

Slave NMH = 0.35 × (VCC – (3 × IL(THREE SLAVES) × RWPU))(EQ. 6d)

The slave rising edge noise margin (slave NMRE) computation is:

Slave NMRE = VTH – VTL(EQ. 7a)

or

Slave NMRE = 0.1 × (IL(THREE SLAVES) × RWPU)).(EQ. 7b)

Table 4. Typical DS28E50 Noise Margins over Temperature

Temperature Master NML (Equation 5) Master NMH (Equation 6) Master NMRE (Equation 7)
25°C 0.65 × (3.3 - (3x10µA × 1136) – 0.03 = 2.09V (3.3V – (3x10µA × 1136)) – 0.4 × 3.3V = 1.946V
55°C (0.4 × 3.3V) – 0.13V = 1.190V (3.3V – (3x23µA × 1119)) – 0.4 × 3.3V = 1.903V
85°C (0.4 × 3.3V) – 0.15V = 1.170V (3.3V – (3x49µA × 1102) – 0.4 × 3.3V = 1.818V

Noise Margin Calculation Summary

In standard speed, in a typical system, the slave rising edge case is not relevant. This is because typical 1-Wire rise time is <500ns, so the period of noise required on the rising edge to trigger this case is much faster than the tREH delay (1/1MHz = 1µs), so the noise is filtered. Thus, we expect to be limited by slave NMH during slave sampling and slave idle. To verify our analysis, we can inject a sine wave at 500KHz and 2MHz. At both frequencies, we expect failure to occur when the sine wave causes the 1-Wire line to dip to (VOH(MASTER) – NMH).

In overdrive speed, the analysis is not as simple. In a system with typical rise times, the period of noise required on the rising edge to trigger the rising edge scenario approaches the length of the tREH delay (1/10MHz = 100ns). Many factors affect rise time, and normal process variation can affect the exact tREH delay. Therefore, performance in overdrive is highly dependent on the noise frequency, the rise time, and the exact tREH delay, all of which determine if performance is limited by the rising edge scenario or by slave NMH. To verify our analysis, we can inject a sine wave at 2MHz, which is too slow to trigger the rising edge case. Similar to the standard speed test, we expect failure to occur when the sine wave causes the 1-Wire line to dip to (VOH(MASTER) – NMH). To test whether the rising edge case can be triggered at all, we can inject a sine wave with 0.75VP-P, which is much greater than slave NMRE, and sweep the frequency up.

Noise Margin Measurements

One method to inject noise into a 1-Wire system is to generate noise connected through a large impedance to the system under test. This method was explored and connected as shown in Figure 4. The full results of the noise margin measurements can be seen in Table 5.

Noise injection test circuitFigure 4. Noise injection test circuit.

Conditions

  • VCC = 3.3V
  • RWPU = 1k
  • DS2477 is set to the medium configuration. Refer to the Electrical Characteristics table in the DS2477 data sheet.
  • Three DS28E50 devices on the 15cm long bus.
  • A PASS is when all three DS28E50 devices are discovered with no bit errors.
  • HP33120A Waveform Generator is set to DC offset 1.65V. This offset centers the sine wave noise around VCC (i.e., 3.3V).
  • The software is set up to discover (i.e., search ROM sequence) all the ROMIDs repeatedly while verifying each time with the memory contents from each DS28E50 ROM Option page.

Table 5. Noise Margin Measurements

Temp
(C)
Freq
(MHz)
Noise
(VOH(MASTER) – VSINEMIN)
RSRC (Ω) Speed Discovery Result
25 0.5 1.00 3.9k STD Pass
1.10 Fail
2 1.00 2.2k Pass
1.04 Fail
55 0.5 1.00 3.9k Pass
1.02 Fail
2 1.00 2.2k Pass
1.02 Fail
85 0.5 1.00 3.9k Pass
1.02 Fail
2 0.94 2.2k Pass
0.98 Fail
25 2 1.00 OVD Pass
1.02 Fail
55 1.00 Pass
1.02 Fail
85 0.98 Pass
1.00 Fail

Each result was measured by positioning the scope cursors. One such measurement is shown in Figure 5. Channel 1 is the 1-Wire bus.

2MHz-sine noise-margin measurement during a STD write for one time slot at 25°CFigure 5. 2MHz-sine noise-margin measurement during a STD write for one time slot at 25°C.

Measured noise limits in Table 5 correlate to typical slave NMH calculations in Table 4 reasonably well, within 4% of VPUP.

In overdrive, an injected sine wave from 5MHz to 15MHz (~0.75VP-P) with 1MHz increments was tried. However, no failures were observed from slave NMRE. This is realistic since the rise time observed was less than 100ns.

Error Detection

Any noise discussion is not complete without mentioning a means of detecting a bit error. 1-Wire utilizes a CRC for error detection, which makes it more robust than other protocols (e.g., I2C, SPI), which have no means of detecting bit errors. CRCs are particularly good at detecting common errors caused by noise. This provides a quick and reasonable assurance that communication is error free. In the event of an occasional error, corrective action such as rereading data or repeating a computation can be taken. For more information on implementing 1-Wire CRCs, refer to the Application Note 27, "Understanding and Using Cyclic Redundancy Checks with Maxim 1-Wire and iButton Products."

Worst Case Analysis

In a worst-case system, long rise times cause the rising edge scenario to dominate, causing noise margin to diminish. In addition, poorly chosen master parameters can cause slave performance to change (e.g., VOL), potentially affecting performance. It is important to finalize the DS2477 master settings and system topology prior to calculating or testing noise immunity to prevent an overly pessimistic result.

DS2477 Active Pullup (APU) Benefits

Though not included in this analysis, the DS2477 APU feature has two significant benefits relative to noise performance. It decreases the rise time of the 1-Wire line, which reduces or eliminates the time that the slave rising edge case is valid. Also, it can significantly reduce the magnitude of noise injected into the system. If noise performance is critical, the APU feature is highly recommended. Figure 6 and Figure 7 shows this difference. Channel 1 is the 1-Wire bus and channel 2 is the DS28E50 CEXT pin to monitor device charge.

Noise injection with no APUFigure 6. Noise injection with no APU.

Noise injection with APUFigure 7. Noise injection with APU.

Summary

This application note provides information on the circuit methods used by 1-Wire devices to operate in noisy system environments. These methods provide excellent immunity performance such that noise levels up to approximately 1V can be tolerated during slave sampling or idle times. The rising-edge hold-off feature effectively filters noise on rising edges in standard speed for typical systems. In overdrive mode, rising-edge hold-off is not as effective but systems with fast rise time still benefit. In conclusion, results confirm that 1-Wire can provide robust and reliable performance in environments with significant noise.