キーワード: SSM, BOC, FDL, Sa bits
関連製品 |
Apart from BITS elements like in the DS26504, DS26503, etc., normal SCTs like the DS26521 and DS2155 can also be used to transmit/receive SSMs. SSMs (synchronization status messages) defined in ANSI (T1.105) and ITU-T (G.703) recommendations identify the quality level of the incoming clock. In T1 mode, these messages are transmitted as bit-oriented codes in the datalink bits; in E1 mode, these are transmitted using one of the five Sa bits. The HDLC controllers present in the device can also be used to transmit or receive an SSM. In addition to the DS2155 and DS26521, this application note can be used to configure SSMs in the DS26514, DS26518, and DS26522 by mapping the registers.
In T1 mode, an SSM is transmitted and received in the DS26521 and DS2155 using two methods:
Even though HDLC controllers could be used for this purpose, using the BOC engine is recommended.
In E1 mode, an SSM is transmitted and received using the five Sa bits. An SSM is valid only when seven out of 10 messages are alike.
Acronyn | Description |
---|---|
BOC | Bit Oriented Code |
CRC | Cyclic Redundancy Check |
FDL | Facilities Data Link |
HDLC | High-Level Data Link Control |
SSM | Synchronization Status Message |
Steps to Transmit a BOC Message
Quality Level | Description | FDL Code Word (DS1 ESF) |
---|---|---|
1 | Stratum 1 traceable | 0 0000100 11111111 |
2 | Synchronized traceability unknown | 0 0000100 11111111 |
3 | Stratum 2 traceable | 0 000110 0 11111111 |
4 | Stratum 3 traceable | 0 0000100 11111111 |
5 | SONET minimum clock traceable | 0 0100010 11111111 |
6 | Stratum 4 traceable | 0 010100 0 11111111 |
7 | Do not use for synchronization | 0 011000 0 11111111 |
User Assignable | Reserved for network synchronization use | 0 100000 0 11111111 |
Figure 1. BOCC control register description.
The host can then read the RFDL register for the received BOC message. Bit 7 of the SR2 register is set if the received BOC message is valid.
On the transmit side, Sa bits can be inserted into the Sa bit control registers (TSACR).
Figure 2. SR4 register description.
Figure 3. THC2 register description.
Figure 4. E1TSa4 register description.
Note: The lower nibble and higher nibble of this register should be loaded with the same SSM code.
Table 2. SSM Codes for E1 OperationQuality Level | Description | San1, San2, San3, San4 (where n = bit number 4, 5, 6, 7, or 8) |
---|---|---|
0 | 0000 | |
1 | 0001 | |
2 | 0010 | |
3 | 0011 | |
4 | 0100 | |
5 | 0101 | |
6 | 0110 | |
7 | 0111 | |
8 | 1000 | |
9 | 1001 | |
10 | 1010 | |
11 | 1011 | |
12 | 1100 | |
13 | 1101 | |
14 | 1110 | |
15 | 1111 |
Figure 5. E1TSa4 register description.
Figure 6. TCR1register description.