キーワード: power modes, transition, EMI, firmware update, power cycling, Teridian, energy meter
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TRIMSEL
) and then reading the corresponding fuse value from I/O RAM register 0x20FF (TRIM
).
extern void trim_test(void) small reentrant; EA = 0; CONFIG0 = 0; // Make sure we are running as fast as we can. IFLAGS = (~IE_PLLFALL_) & (~IE_PLLRISE_); // force an edge to occur WAKE = 0x81; // force a wake timer wake if sleep is forced trim_test(); // From start-up code.
;/*************************************************************************** ; * This code and information is provided "as is" without warranty of any * ; * kind, either expressed or implied, including but not limited to the * ; * implied warranties of merchantability and/or fitness for a particular * ; * purpose. * ; * * ; * Copyright (C) 2011 Maxim Integrated All Rights Reserved. * ; ***************************************************************************/ ;//************************************************************************** ;// ;// DESCRIPTION: 71M652x POWER METER - STARTUP Code. ;// ;//************************************************************************** ;// ;// File: STARTUP_N_SAFE.A51. ;// $NOMOD51 ;------------------------------------------------------------------------------ ; This file is part of the C51 Compiler package ; Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc. ;------------------------------------------------------------------------------ ; STARTUP.A51: This code is executed after processor reset. ; ; To translate this file use A51 with the following invocation: ; ; A51 STARTUP_N_SAFE.A51 ; ; To link the modified STARTUP_N_SAFE.OBJ file to your application use the following ; BL51 invocation: ; ; BL51 <your object file list>, STARTUP_N_SAFE.OBJ <controls> ; ;------------------------------------------------------------------------------ ; ; User-defined Power-On Initialization of Memory ; With the following EQU statements the initialization of memory ; at processor reset can be defined: ; ; ; the absolute start-address of IDATA memory is always 0 IDATALEN EQU 100H ; the length of IDATA memory in bytes. ; XDATASTART EQU 0H ; the absolute start-address of XDATA memory XDATALEN EQU 000H ; the length of XDATA memory in bytes. ; PDATASTART EQU 0H ; the absolute start-address of PDATA memory PDATALEN EQU 0H ; the length of PDATA memory in bytes. ; ; Notes: The IDATA space overlaps physically the DATA and BIT areas of the ; 8051 CPU. At minimum the memory space occupied from the C51 ; run-time routines must be set to zero. ;------------------------------------------------------------------------------ ; ; Reentrant Stack Initialization ; ; The following EQU statements define the stack pointer for reentrant ; functions and initialized it: ; ; Stack Space for reentrant functions in the SMALL model. IBPSTACK EQU 1 ; set to 1 if small reentrant is used. IBPSTACKTOP EQU 0FFH+1 ; set top of stack to highest location+1. ; ; Stack Space for reentrant functions in the LARGE model. XBPSTACK EQU 0 ; set to 1 if large reentrant is used. XBPSTACKTOP EQU 07FFH+1; set top of stack to highest location+1. ; ; Stack Space for reentrant functions in the COMPACT model. PBPSTACK EQU 0 ; set to 1 if compact reentrant is used. PBPSTACKTOP EQU 07FFH+1; set top of stack to highest location+1. ; ;------------------------------------------------------------------------------ ; Page Definition for Using the Compact Model with 64 KByte xdata RAM ; ; The following EQU statements define the xdata page used for pdata ; variables. The EQU PPAGE must conform with the PPAGE control used ; in the linker invocation. ; PPAGEENABLE EQU 1 ; set to 1 if pdata object are used. ; PPAGE EQU 7 ; define PPAGE number. PUBLIC PPAGE_SFR PPAGE_SFR DATA 0BFH ; SFR that supplies uppermost address byte ; (most 8051 variants use P2 as uppermost address byte) ;------------------------------------------------------------------------------ ; Switch to M6520 when chip is available. ; Standard SFR Symbols ACC DATA 0E0H B DATA 0F0H SP DATA 81H DPL DATA 82H DPH DATA 83H USER1 DATA 90H DIR1 DATA 91H FCTRL DATA 0B2H IPH DATA 0B9H IPL DATA 0A9H IRCON DATA 0C0H IEN0 DATA 0A8H IEN1 DATA 0B8H NAME ?C_STARTUP ?C_C51STARTUP SEGMENT CODE ?STACK SEGMENT IDATA RSEG ?STACK DS 1 EXTRN CODE (?C_START) PUBLIC ?C_STARTUP PUBLIC _?TRIM_TEST CSEG AT 0 ?C_STARTUP: LJMP STARTUP1 RSEG ?C_C51STARTUP STARTUP1: CLR IEN0^7 ; Disable interrupts ; To enable secure mode, remove the semicolon of the next line ; ORL FCTRL,#40H ; set secure bit MOV 0E8h,#0FFh ; Refresh nonmaskable watchdog. ; Set system interrupt priorities; more frequent are higher priority. MOV IPH,#01DH ; From code in options_gbl.h, main.c MOV IPL,#00AH ; From code in options_gbl.h ; Clear PLL_OK interrupt (bit3), and others MOV IRCON,#0 ; Enable PLL_OK interrupt MOV DPTR,#2007H ; Set EX_PLL MOV A,#20H MOVX @DPTR,A ; Enable interrupts MOV IEN1,#08H ; Enable INT4, the PLL_OK interrupt MOV IEN0,#80H ; Enable all interrupts ACALL _?TRIM_TEST ; Test 6521's trims IF IDATALEN <> 0 MOV R0,#IDATALEN - 1 CLR A IDATALOOP: MOV @R0,A DJNZ R0,IDATALOOP ENDIF IF XDATALEN <> 0 MOV DPTR,#XDATASTART MOV R7,#LOW (XDATALEN) IF (LOW (XDATALEN)) <> 0 MOV R6,#(HIGH (XDATALEN)) +1 ELSE MOV R6,#HIGH (XDATALEN) ENDIF CLR A XDATALOOP: MOVX @DPTR,A INC DPTR DJNZ R7,XDATALOOP DJNZ R6,XDATALOOP ENDIF IF PPAGEENABLE <> 0 MOV PPAGE_SFR,#PPAGE ENDIF IF PDATALEN <> 0 MOV R0,#LOW (PDATASTART) MOV R7,#LOW (PDATALEN) CLR A PDATALOOP: MOVX @R0,A INC R0 DJNZ R7,PDATALOOP ENDIF IF IBPSTACK <> 0 EXTRN DATA (?C_IBP) MOV ?C_IBP,#LOW IBPSTACKTOP ENDIF IF XBPSTACK <> 0 EXTRN DATA (?C_XBP) MOV ?C_XBP,#HIGH XBPSTACKTOP MOV ?C_XBP+1,#LOW XBPSTACKTOP ENDIF IF PBPSTACK <> 0 EXTRN DATA (?C_PBP) MOV ?C_PBP,#LOW PBPSTACKTOP ENDIF MOV SP,#?STACK-1 LJMP ?C_START ; Read a trim whose index is in A. Return the trim in A. CSEG AT 100H FUSE_TABLE: DB 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff ; Trim test. Prefix "_?" tells Keil C it's reentrant. _?TRIM_TEST: PUSH IEN0 PUSH PSW ; Save registers, so it's reentrant. MOV PSW,00H ; Select registers before saving them PUSH DPL PUSH DPH PUSH ACC MOV A,R7 ; Save R7 from the current register set. PUSH ACC MOV A,R6 ; Save R6 from the current register set. PUSH ACC CLR IEN0.7 ; Wait for all fuses to be read once before checking fuses ; Complete fuse read takes 45 xtal clock cycles (1 fuse per xtal clock) MOV R7,#21 ; Wait 21x4 = 48 cycles loop_inner: DJNZ R7,loop_inner ; 4 cycles (in brownout, 1 cycle/clk) mov DPH, #HIGH(FUSE_TABLE) fuse_test_frst: ; check if values previously stored mov DPL,#LOW(FUSE_TABLE) clr a movc a,@a+dptr ; read fuse table xrl a,#55H jnz fuse_save MOV DPTR,#2003H ; Check if in brownout mode MOVX A,@DPTR JB ACC.6,PASS ; Mission mode, so don't check. fuse_test: mov r7,#8 ; byte counter fuse_test_lp1: mov DPTR,#FUSE_TABLE ; load pointer to fuse table mov a,r7 movc a,@a+dptr ; read fuse table mov r6,a mov a,r7 MOV DPTR,#20FDH ; TRIMSEL address MOVX @DPTR,A ; load reg to read trim MOV DPL,#0FFH ; TRIM value address MOVX A,@DPTR ; Get trim value cjne a,06H,FAIL ; test if flash read and trim == djnz r7,fuse_test_lp1 JMP PASS fuse_save: MOV DPTR,#2003H ; Check if in brownout mode MOVX A,@DPTR ; If brownout mode, don't save them and enter sleep. JNB ACC.6,FAIL ; mov 84H,#LOW(FUSE_TABLE) mov r7,#8 ; byte counter fuse_save_lp1: mov a,r7 MOV DPTR,#20FDH ; TRIMSEL address MOVX @DPTR,A ; load reg to read trim MOV DPL,#0FFH ; TRIM value address MOVX A,@DPTR ; Get trim value mov r6,a mov a,r7 mov dptr,#FUSE_TABLE add a,DPL mov DPL,a mov a,r6 orl 0B2H,#01H ; set to flash write movx @dptr,a ; write fuse table byte djnz r7,fuse_save_lp1 mov a,#55H ; control byte to mark mov dptr,#FUSE_TABLE orl 0B2H,#01H ; set to flash write movx @dptr,a ; write fuse table byte jmp PASS FAIL: MOV DPTR,#20A9H ; WAKE address MOV A,#0C1H ; SLEEP forces wake and fuse re-read MOVX @DPTR,A PASS: CLR A ; Select 0 MOV DPTR,#20FDH ; TRIMSEL address MOVX @DPTR,A ; clear trim select register. POP ACC MOV R6,A ; Restore R7 in this register set POP ACC MOV R7,A ; Restore R7 in this register set POP ACC POP DPH POP DPL POP PSW ; Restore registers, so it's reentrant. POP IEN0 RET END