A similar version of this article appeared in the September 3, 2007 issue of EDN
The following describes a simple alternative to the non-volatile gating function typically implemented by a PAL, GAL, or CPLD device. To "gate" a logic signal (to block or transmit it), you usually employ a logic gate such as an AND gate, and use the gate's second input to define whether the gate blocks or transmits the applied signal (Figure 1
). Because logic gates perform immediate Boolean operations, their operations are combinational, and without memory.
Figure 1. AND Gate used to gate a signal.
If one needs to program a gate that should always either block or transmit the signal after system start-up, you must store the "transmit/block" logic state in some form of non-volatile memory. Two basic methods are available for storing such logic states. The first involves a microcontroller in combination with non-volatile memory such as an EEPROM. This method is suitable if the system can wait until the microcontroller reads the logic state from memory and applies it to a hardware pin (typically via a GPIO pin). Some systems, however, require that the transmit/block signal be present at start-up. For those, the read delay from memory is not acceptable.
A second method, useful for systems without a µC or that cannot wait for the µC to read from memory at boot time, stores the logic state in a device that makes it immediately available at power-up. Typical programmable-logic devices for this purpose are the PAL, GAL, or CPLD, which implement the gating function in combination with programmable non-volatile memory. These devices offer much more than gating with memory, however, and may be over-qualified for systems that need only a few such gates. Also their packages are relatively large, to accomodate the many logic-I/O pins they offer.
If you need only a few non-volatile gates, consider using a component common in analog and mixed-signal systems—the digital potentiometer, or DigiPot (Figure 2
). Ground the L-end of the resistor string, and route the signal into the H-end of the string. Then, the wiper output is either shorted to ground for blocking, or connected to the input signal for transmission (Figures 3
). These connections program the DigiPot for only two of its N possible states: D∈[1,N], where N = number of taps.
Figure 2. DigiPot used for gating.
Figure 3. DigiPot in transmission.
Figure 4. DigiPot in blocking.
You can program the DigiPot via its serial interface, during board or system test. The up/down interface found on some DigiPots is suitable for that purpose. When selecting a non-volatile DigiPot, the following criteria should be considered:
- DigiPots typically have 32 or more taps (you need at least two). A DigiPot wiper has a resistance associated with the internal switches, and should be as small as possible to avoid distorting the switching signal. A typical wiper resistance is 100Ω to 1kΩ (for the MAX5527, wiper resistance measures a low 90Ω).
- Because the resistance of a DigiPot wiper decreases with increasing supply voltage, you should select a high supply voltage for the DigiPot.
- To minimize loading on the signal source and not limit the DigiPot's signal bandwidth, you should select a DigiPot with a high end-to-end resistance. 100kΩ is acceptable for many applications.
- Select a non-volatile DigiPot if the gate's state must be programmed in non-volatile memory. Some DigiPots have an OTP (one time programming) capability, which allows you to save the wiper's setting once and for all. OTP is suitable when you don't expect to make later changes in the gating function. The number of gates for which the state must be stored determines the number of DigiPots, which are available in arrays of 1 to 6 (and more) per package.
DigiPot bandwidth determines the maximum data rate for signals transmitted through the DigiPot. If the switching rate of these applied logic signals is too high for the DigiPots available, you can use a conventional (high speed) logic gate with the transmit/block input controlled by a DigiPot (Figure 5
Figure 5. Non-volatile gating of high-speed signals.