The following table shows the pins that are available on DS21Q55, DS21Q50, and DS21Q59.
NAME |
TYPE |
FUNCTION |
DS21Q55 |
DS21Q50/59 |
4/8/16MCK |
O |
4.096MHz, 8.192MHz, or 16.384 MHz Clock |
|
X |
A0-A4 |
I |
Address Bus Bit 0 (LSB) to Address Bus Bit 4 |
X |
X |
A5/ALE(AS) |
I |
Address Bus Bit 5 (MSB)/Address Latch Enable |
|
X |
A5, A6 |
I |
Address Bus Bit 5 to Address Bus Bit 6 |
X |
|
A7/ALE(AS) |
I |
Address Bus Bit 7 (MSB)/Address Latch Enable |
X |
|
AJACKI |
I |
Alternate Jitter Attenuator Clock Input |
|
X |
AJACKO |
O |
Alternate Jitter Attenuator Clock Output |
|
X |
BPCLK1 |
O |
Back Plane Clock, Transceiver 1 |
X |
|
BPCLK2 |
O |
Back Plane Clock, Transceiver 2 |
X |
|
BPCLK3 |
O |
Back Plane Clock, Transceiver 3 |
X |
|
BPCLK4 |
O |
Back Plane Clock, Transceiver 4 |
X |
|
BTS0 |
I |
Bus Type Select 0 |
|
X |
BTS1 |
I |
Bus Type Select |
|
X |
BTS |
I |
Bus Type Select (0 = Intel® / 1 = Motorola®) |
X |
|
CS |
I |
Chip Select |
|
X |
CS1 |
I |
Chip Select, Transceiver 1 |
X |
|
CS2 |
I |
Chip Select, Transceiver 2 |
X |
|
CS3 |
I |
Chip Select, Transceiver 3 |
X |
|
CS4 |
I |
Chip Select, Transceiver 4 |
X |
|
D0/AD0- |
I/O |
Data Bus Bit 0/Address/Data Bus Bit 0 (LSB) to Data |
X |
X |
D7/AD7 |
|
Bus Bit 7/Address/Data Bus Bit 7 (MSB) |
|
|
DVDD1 |
-- |
Digital Positive Supply |
X (Note 1) |
X |
DVDD2 |
-- |
Digital Positive Supply |
X (Note 1) |
X |
DVDD3 |
-- |
Digital Positive Supply |
X (Note 1) |
X |
DVDD4 |
-- |
Digital Positive Supply |
X (Note 1) |
X |
DVSS1 |
-- |
Digital Signal Ground |
X (Note 2) |
X |
DVSS2 |
-- |
Digital Signal Ground |
X (Note 2) |
X |
DVSS3 |
-- |
Digital Signal Ground |
X (Note 2) |
X |
DVSS4 |
-- |
Digital Signal Ground |
X (Note 2) |
X |
ESIBRD1 |
-- |
Extended System Information Bus Read, Transceiver 1 |
X |
|
ESIBRD2 |
-- |
Extended System Information Bus Read, Transceiver 2 |
X |
|
ESIBRD3 |
-- |
Extended System Information Bus Read, Transceiver 3 |
X |
|
ESIBRD4 |
-- |
Extended System Information Bus Read, Transceiver 4 |
X |
|
ESIBS0_1 |
I/O |
Extended System Information Bus 0, Transceiver 1 |
X |
|
ESIBS0_2 |
I/O |
Extended System Information Bus 0, Transceiver 2 |
X |
|
ESIBS0_3 |
I/O |
Extended System Information Bus 0, Transceiver 3 |
X |
|
ESIBS0_4 |
I/O |
Extended System Information Bus 0, Transceiver 4 |
X |
|
ESIBS1_1 |
I/O |
Extended System Information Bus 1, Transceiver 1 |
X |
|
ESIBS1_2 |
I/O |
Extended System Information Bus 1, Transceiver 2 |
X |
|
ESIBS1_3 |
I/O |
Extended System Information Bus 1, Transceiver 3 |
X |
|
ESIBS1_4 |
I/O |
Extended System Information Bus 1, Transceiver 4 |
X |
|
INT |
O |
Interrupt |
X |
X |
JTCLK |
I |
JTAG Clock |
X |
|
JTDI |
I |
JTAG Data Input, Transceiver 1 |
X |
|
JTDO |
O |
JTAG Data Output, Transceiver 4 |
X |
|
JTMS |
I |
JTAG Test Mode Select |
X |
|
JTRST |
I |
JTAG Reset |
X |
|
LIUC |
I |
Line Interface Connect |
X |
|
MCLK |
I |
Master Clock Input |
|
X |
MCLK1 |
I |
Master Clock, Transceiver 1 and Transceiver 3 |
X |
|
MCLK2 |
I |
Master Clock, Transceiver 2 and Transceiver 4 |
X |
|
MUX |
I |
Mux Bus Select |
X |
|
OUTA1 |
O |
User Selectable Output A |
|
X |
OUTA2 |
O |
User Selectable Output A |
|
X |
OUTA3 |
O |
User Selectable Output A |
|
X |
OUTA4 |
O |
User Selectable Output A |
|
X |
OUTB1 |
O |
User Selectable Output B |
|
X |
OUTB2 |
O |
User Selectable Output B |
|
X |
OUTB3 |
O |
User Selectable Output B |
|
X |
OUTB4 |
O |
User Selectable Output B |
|
X |
PBTS |
I |
Parallel Bus Type Select |
|
X |
RCHBLK1 |
O |
Receive Channel Block, Transceiver #1. |
X |
|
RCHBLK2 |
O |
Receive Channel Block, Transceiver #2. |
X |
|
RCHBLK3 |
O |
Receive Channel Block, Transceiver #3. |
X |
|
RCHBLK4 |
O |
Receive Channel Block, Transceiver #4. |
X |
|
RCHCLK1 |
O |
Receive Channel Clock, Transceiver #1. |
X |
|
RCHCLK2 |
O |
Receive Channel Clock, Transceiver #2. |
X |
|
RCHCLK3 |
O |
Receive Channel Clock, Transceiver #3. |
X |
|
RCHCLK4 |
O |
Receive Channel Clock, Transceiver #4. |
X |
|
RCLK1 |
O |
Receive Clock Output from the Framer, Transceiver #1. |
X |
|
RCLK2 |
O |
Receive Clock Output from the Framer, Transceiver #2. |
X |
|
RCLK3 |
O |
Receive Clock Output from the Framer, Transceiver #3. |
X |
|
RCLK4 |
O |
Receive Clock Output from the Framer, Transceiver #4. |
X |
|
RCLKI1 |
I |
Receive Clock Input for the LIU, Transceiver #1. |
X |
|
RCLKI2 |
I |
Receive Clock Input for the LIU, Transceiver #2. |
X |
|
RCLKI3 |
I |
Receive Clock Input for the LIU, Transceiver #3. |
X |
|
RCLKI4 |
I |
Receive Clock Input for the LIU, Transceiver #4. |
X |
|
RCLKO1 |
O |
Receive Clock Output from the LIU, Transceiver #1. |
X |
|
RCLKO2 |
O |
Receive Clock Output from the LIU, Transceiver #2. |
X |
|
RCLKO3 |
O |
Receive Clock Output from the LIU, Transceiver #3. |
X |
|
RCLKO4 |
O |
Receive Clock Output from the LIU, Transceiver #4. |
X |
|
RD*(DS*) |
I |
Read Input (Data Strobe) |
X |
X |
REFCLK |
I/O |
Reference Clock |
|
X |
RFSYNC1 |
O |
Receive Frame Sync (before the receive elastic store), Transceiver #1. |
X |
|
RFSYNC2 |
O |
Receive Frame Sync (before the receive elastic store), Transceiver #2. |
X |
|
RFSYNC3 |
O |
Receive Frame Sync (before the receive elastic store), Transceiver #3. |
X |
|
RFSYNC4 |
O |
Receive Frame Sync (before the receive elastic store), Transceiver #4. |
X |
|
RLCLK1 |
O |
Receive Link Clock, Transceiver #1. |
X |
|
RLCLK2 |
O |
Receive Link Clock, Transceiver #2. |
X |
|
RLCLK3 |
O |
Receive Link Clock, Transceiver #3. |
X |
|
RLCLK4 |
O |
Receive Link Clock, Transceiver #4. |
X |
|
RLINK1 |
O |
Receive Link Data, Transceiver #1. |
X |
|
RLINK2 |
O |
Receive Link Data, Transceiver #2. |
X |
|
RLINK3 |
O |
Receive Link Data, Transceiver #3. |
X |
|
RLINK4 |
O |
Receive Link Data, Transceiver #4. |
X |
|
RLOS/LOTC1 |
O |
Receive Loss of Sync / Loss Of Transmit Clock, Transceiver #1. |
X |
|
RLOS/LOTC2 |
O |
Receive Loss of Sync / Loss Of Transmit Clock, Transceiver #2. |
X |
|
RLOS/LOTC3 |
O |
Receive Loss of Sync / Loss Of Transmit Clock, Transceiver #3. |
X |
|
RLOS/LOTC4 |
O |
Receive Loss of Sync / Loss Of Transmit Clock, Transceiver #4. |
X |
|
RMSYNC1 |
O |
Receive Multiframe Sync, Transceiver #1. |
X |
|
RMSYNC2 |
O |
Receive Multiframe Sync, Transceiver #2. |
X |
|
RMSYNC3 |
O |
Receive Multiframe Sync, Transceiver #3. |
X |
|
RMSYNC4 |
O |
Receive Multiframe Sync, Transceiver #4. |
X |
|
RNEGI1 |
I |
Receive Negative Data for the Framer, Transceiver #1. |
X |
|
RNEGI2 |
I |
Receive Negative Data for the Framer, Transceiver #2. |
X |
|
RNEGI3 |
I |
Receive Negative Data for the Framer, Transceiver #3. |
X |
|
RNEGI4 |
I |
Receive Negative Data for the Framer, Transceiver #4. |
X |
|
RNEGO1 |
O |
Receive Negative Data from the LIU, Transceiver #1. |
X |
|
RNEGO2 |
O |
Receive Negative Data from the LIU, Transceiver #2. |
X |
|
RNEGO3 |
O |
Receive Negative Data from the LIU, Transceiver #3. |
X |
|
RNEGO4 |
O |
Receive Negative Data from the LIU, Transceiver #4. |
X |
|
RPOSI1 |
I |
Recekve Positive Data for the Framer, Transceiver #1. |
X |
|
RPOSI2 |
I |
Recekve Positive Data for the Framer, Transceiver #2. |
X |
|
RPOSI3 |
I |
Recekve Positive Data for the Framer, Transceiver #3. |
X |
|
RPOSI4 |
I |
Recekve Positive Data for the Framer, Transceiver #4. |
X |
|
RPOSO1 |
O |
Receive Positive Data from the LIU, Transceiver #1. |
X |
|
RPOSO2 |
O |
Receive Positive Data from the LIU, Transceiver #2. |
X |
|
RPOSO3 |
O |
Receive Positive Data from the LIU, Transceiver #3. |
X |
|
RPOSO4 |
O |
Receive Positive Data from the LIU, Transceiver #4. |
X |
|
RRING1 |
I |
Receive Analog Ring Input, Transceiver #1. |
X |
X |
RRING2 |
I |
Receive Analog Ring Input, Transceiver #2. |
X |
X |
RRING3 |
I |
Receive Analog Ring Input, Transceiver #3. |
X |
X |
RRING4 |
I |
Receive Analog Ring Input, Transceiver #4. |
X |
X |
RSER1 |
O |
Receive Serial Data, Transceiver #1. |
X |
X |
RSER2 |
O |
Receive Serial Data, Transceiver #2. |
X |
X |
RSER3 |
O |
Receive Serial Data, Transceiver #3. |
X |
X |
RSER4 |
O |
Receive Serial Data, Transceiver #4. |
X |
X |
RSIG1 |
O |
Receive Signaling Output, Transceiver #1. |
X |
|
RSIG2 |
O |
Receive Signaling Output, Transceiver #2. |
X |
|
RSIG3 |
O |
Receive Signaling Output, Transceiver #3. |
X |
|
RSIG4 |
O |
Receive Signaling Output, Transceiver #4. |
X |
|
RSIGF1 |
O |
Receive Signaling Freeze Output, Transceiver #1. |
X |
|
RSIGF2 |
O |
Receive Signaling Freeze Output, Transceiver #2. |
X |
|
RSIGF3 |
O |
Receive Signaling Freeze Output, Transceiver #3. |
X |
|
RSIGF4 |
O |
Receive Signaling Freeze Output, Transceiver #4. |
X |
|
RSYNC1 |
I/O |
Receive Sync, Transceiver #1. |
X |
X |
RSYNC2 |
I/O |
Receive Sync, Transceiver #2. |
X |
X |
RSYNC3 |
I/O |
Receive Sync, Transceiver #3. |
X |
X |
RSYNC4 |
I/O |
Receive Sync, Transceiver #4. |
X |
X |
RSYSCLK1 |
I |
Receive System Clock, Transceiver #1. |
X |
|
RSYSCLK2 |
I |
Receive System Clock, Transceiver #2. |
X |
|
RSYSCLK3 |
I |
Receive System Clock, Transceiver #3. |
X |
|
RSYSCLK4 |
I |
Receive System Clock, Transceiver #4. |
X |
|
RTIP1 |
I |
Receive Analog Tip Input, Transceiver #1. |
X |
X |
RTIP2 |
I |
Receive Analog Tip Input, Transceiver #2. |
X |
X |
RTIP3 |
I |
Receive Analog Tip Input, Transceiver #3. |
X |
X |
RTIP4 |
I |
Receive Analog Tip Input, Transceiver #4. |
X |
X |
RVDD1 |
-- |
Receive Analog Positive Supply. |
X |
X |
RVDD2 |
-- |
Receive Analog Positive Supply. |
X |
X |
RVDD3 |
-- |
Receive Analog Positive Supply. |
X |
X |
RVDD4 |
-- |
Receive Analog Positive Supply. |
X |
X |
RVSS1 |
-- |
Receive Analog Signal Ground |
X (Note 3) |
X |
RVSS2 |
-- |
Receive Analog Signal Ground |
X (Note 3) |
X |
RVSS3 |
-- |
Receive Analog Signal Ground |
X (Note 3) |
X |
RVSS4 |
-- |
Receive Analog Signal Ground |
X (Note 3) |
X |
SYSCLK1 |
I |
Transmit/Receive System Clock |
|
X |
SYSCLK2 |
I |
Transmit/Receive System Clock |
|
X |
SYSCLK3 |
I |
Transmit/Receive System Clock |
|
X |
SYSCLK4 |
I |
Transmit/Receive System Clock |
|
X |
TCHBLK1 |
O |
Transmit Channel Block, Transceiver #1. |
X |
|
TCHBLK2 |
O |
Transmit Channel Block, Transceiver #2. |
X |
|
TCHBLK3 |
O |
Transmit Channel Block, Transceiver #3. |
X |
|
TCHBLK4 |
O |
Transmit Channel Block, Transceiver #4. |
X |
|
TCHCLK1 |
O |
Transmit Channel Clock, Transceiver #1. |
X |
|
TCHCLK2 |
O |
Transmit Channel Clock, Transceiver #2. |
X |
|
TCHCLK3 |
O |
Transmit Channel Clock, Transceiver #3. |
X |
|
TCHCLK4 |
O |
Transmit Channel Clock, Transceiver #4. |
X |
|
TCLK1 |
I |
Transmit Clock, Transceiver #1. |
X |
X |
TCLK2 |
I |
Transmit Clock, Transceiver #2. |
X |
X |
TCLK3 |
I |
Transmit Clock, Transceiver #3. |
X |
X |
TCLK4 |
I |
Transmit Clock, Transceiver #4. |
X |
X |
TCLKI1 |
I |
Transmit Clock Input for the LIU, Transceiver #1. |
X |
|
TCLKI2 |
I |
Transmit Clock Input for the LIU, Transceiver #2. |
X |
|
TCLKI3 |
I |
Transmit Clock Input for the LIU, Transceiver #3. |
X |
|
TCLKI4 |
I |
Transmit Clock Input for the LIU, Transceiver #4. |
X |
|
TCLKO1 |
O |
Transmit Clock Output from the Framer, Transceiver #1. |
X |
|
TCLKO2 |
O |
Transmit Clock Output from the Framer, Transceiver #2. |
X |
|
TCLKO3 |
O |
Transmit Clock Output from the Framer, Transceiver #3. |
X |
|
TCLKO4 |
O |
Transmit Clock Output from the Framer, Transceiver #4. |
X |
|
TLCLK1 |
O |
Transmit Link Clock, Transceiver #1. |
X |
|
TLCLK2 |
O |
Transmit Link Clock, Transceiver #2. |
X |
|
TLCLK3 |
O |
Transmit Link Clock, Transceiver #3. |
X |
|
TLCLK4 |
O |
Transmit Link Clock, Transceiver #4. |
X |
|
TLINK1 |
I |
Transmit Link Data, Transceiver #1. |
X |
|
TLINK2 |
I |
Transmit Link Data, Transceiver #2. |
X |
|
TLINK3 |
I |
Transmit Link Data, Transceiver #3. |
X |
|
TLINK4 |
I |
Transmit Link Data, Transceiver #4. |
X |
|
TNEGI1 |
I |
Transmit Negative Data Input for the LIU, Transceiver #1. |
X |
|
TNEGI2 |
I |
Transmit Negative Data Input for the LIU, Transceiver #2. |
X |
|
TNEGI3 |
I |
Transmit Negative Data Input for the LIU, Transceiver #3. |
X |
|
TNEGI4 |
I |
Transmit Negative Data Input for the LIU, Transceiver #4. |
X |
|
TNEGO1 |
O |
Transmit Negative Data Output from Framer, Transceiver #1. |
X |
|
TNEGO2 |
O |
Transmit Negative Data Output from Framer, Transceiver #2. |
X |
|
TNEGO3 |
O |
Transmit Negative Data Output from Framer, Transceiver #3. |
X |
|
TNEGO4 |
O |
Transmit Negative Data Output from Framer, Transceiver #4. |
X |
|
TPOSI1 |
I |
Transmit Positive Data Input for the LIU, Transceiver #1. |
X |
|
TPOSI2 |
I |
Transmit Positive Data Input for the LIU, Transceiver #2. |
X |
|
TPOSI3 |
I |
Transmit Positive Data Input for the LIU, Transceiver #3. |
X |
|
TPOSI4 |
I |
Transmit Positive Data Input for the LIU, Transceiver #4. |
X |
|
TPOSO1 |
O |
Transmit Positive Data Output from Framer, Transceiver #1. |
X |
|
TPOSO2 |
O |
Transmit Positive Data Output from Framer, Transceiver #2. |
X |
|
TPOSO3 |
O |
Transmit Positive Data Output from Framer, Transceiver #3. |
X |
|
TPOSO4 |
O |
Transmit Positive Data Output from Framer, Transceiver #4. |
X |
|
TRING1 |
O |
Transmit Analog Ring Output, Transceiver #1. |
X |
X |
TRING2 |
O |
Transmit Analog Ring Output, Transceiver #2. |
X |
X |
TRING3 |
O |
Transmit Analog Ring Output, Transceiver #3. |
X |
X |
TRING4 |
O |
Transmit Analog Ring Output, Transceiver #4. |
X |
X |
TS0 |
I |
Transceiver Select 0 |
|
X |
TS1 |
I |
Transceiver Select 1 |
|
X |
TSER1 |
I |
Transmit Serial Data, Transceiver #1. |
X |
X |
TSER2 |
I |
Transmit Serial Data, Transceiver #2. |
X |
X |
TSER3 |
I |
Transmit Serial Data, Transceiver #3. |
X |
X |
TSER4 |
I |
Transmit Serial Data, Transceiver #4. |
X |
X |
TSIG1 |
I |
Transmit Signaling Input, Transceiver #1. |
X |
|
TSIG2 |
I |
Transmit Signaling Input, Transceiver #2. |
X |
|
TSIG3 |
I |
Transmit Signaling Input, Transceiver #3. |
X |
|
TSIG4 |
I |
Transmit Signaling Input, Transceiver #4. |
X |
|
TSSYNC1 |
I |
Transmit System Sync, Transceiver #1. |
X |
|
TSSYNC2 |
I |
Transmit System Sync, Transceiver #2. |
X |
|
TSSYNC3 |
I |
Transmit System Sync, Transceiver #3. |
X |
|
TSSYNC4 |
I |
Transmit System Sync, Transceiver #4. |
X |
|
TSTRST |
I |
Test/Reset |
X |
|
TSYNC1 |
I/O |
Transmit Sync, Transceiver #1. |
X |
X |
TSYNC2 |
I/O |
Transmit Sync, Transceiver #2. |
X |
X |
TSYNC3 |
I/O |
Transmit Sync, Transceiver #3. |
X |
X |
TSYNC4 |
I/O |
Transmit Sync, Transceiver #4. |
X |
X |
TSYSCLK1 |
I |
Transmit System Clock, Transceiver #1. |
X |
|
TSYSCLK2 |
I |
Transmit System Clock, Transceiver #2. |
X |
|
TSYSCLK3 |
I |
Transmit System Clock, Transceiver #3. |
X |
|
TSYSCLK4 |
I |
Transmit System Clock, Transceiver #4. |
X |
|
TTIP1 |
O |
Transmit Analog Tip Output, Transceiver #1. |
X |
X |
TTIP2 |
O |
Transmit Analog Tip Output, Transceiver #2. |
X |
X |
TTIP3 |
O |
Transmit Analog Tip Output, Transceiver #3. |
X |
X |
TTIP4 |
O |
Transmit Analog Tip Output, Transceiver #4. |
X |
X |
TVDD1 |
-- |
Transmit Analog Positive Supply. |
X |
X |
TVDD2 |
-- |
Transmit Analog Positive Supply. |
X |
X |
TVDD3 |
-- |
Transmit Analog Positive Supply. |
X |
X |
TVDD4 |
-- |
Transmit Analog Positive Supply. |
X |
X |
TVSS1 |
-- |
Transmit Analog Signal Ground. |
X |
X |
TVSS2 |
-- |
Transmit Analog Signal Ground. |
X |
X |
TVSS3 |
-- |
Transmit Analog Signal Ground. |
X |
X |
TVSS4 |
-- |
Transmit Analog Signal Ground. |
X |
X |
WR* (R/W*) |
I |
Write Input (Read/Write) |
X |
X |
DS21Q55 can do all the functional operations that DS21Q50 and DS21Q59 can do. Below are the functions that DS2155 can perform but DS21Q50 or DS21Q59 can not perform.
Most of the registers are the same between the DS21Q50 and DS21Q59. Since the DS21Q59 support CAS/CCS signalling, so it has some extra registers that are not available on DS21Q50.
These Signaling Access Registers are not available on DS21Q50. Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter. The user can read what was written to the transmit signaling buffer by setting CCR6.5 = 1, then reading SA1 - SA16. In most applications however, CCR6.5 should be set = 0.
Signaling data is sampled from time slot 16 in the receive data stream and copied into the receive signaling buffers. The host can access the signaling data by reading SA1 through SA16. The signaling information in these registers is always updated on multiframe boundaries. The SR2.7 bit in Status Register 2 can be used to alert the host that new signaling data is present in the receive signaling buffers. The host has 2ms to read the signaling buffers before they are updated.
Insertion of signaling data from the transmit signaling buffers is enabled by setting CCR6.3 = 1. Signaling data is loaded into the transmit-signaling buffers by writing the signaling data to SA1 - SA16. On multiframe boundaries, the contents of the transmit signaling buffer is loaded into a shift register for placement in the appropriate bit position in the outgoing data stream. The user can utilize the transmit multiframe interrupt in status register 2 (SR2.5) to know when to update the signaling bits. The host has 2ms to update the signaling data. The user only needs to update the signaling data that has changed since the last update.
For CAS mode, the user must provide the CAS alignment pattern (4 zeros in the upper nibble of TS16). Typically this is done by setting the upper 4 bits of SA1 = 0. The lower four bits are alarm bits. The user only needs to update the appropriate channel associated signaling data in SA2 - SA16 on multiframe boundaries.
For the DS21Q50, the operation of the DS21Q50 is configured via a set of seven control registers. The DS21Q50 has only five Common Control Registers (CCR1 to CCR5).
The device Identification Register (IDR) is at address 0Fh. The MSB of this read-only register is fixed to a one indicating that an E1 Quad Transceiver is present. The next 3 MSBs are reserved for future use. The lower 4 bits of the device ID register are used to identify the revision of the device. This register exists in Transceiver #1 only. (TS0, TS1 = 0)
The Test registers at addresses 1E, 1F, and 2F hex are used by the factory in testing the DS21Q50. On power-up, the Test registers should be set to 00h in order for the DS21Q50 to operate properly.