キーワード: アナログ-ディジタルコンバータ, ADC, A/Dコンバータ, 信号品質, シグナルインテグリティ, ハイスピード, 高速, 基板レイアウト, デカップリング, バイパス, プリント基板, 部品配置, インダクタンス, サーマル, 熱, インピーダンス, トレース, 経由, バランス, EDGE, ・ maxlength=
関連製品 |
Pin | Name | Function |
1, 4, 5, 9, 13, 14, 17 | GND | Converter Ground. Connect all ground pins and the exposed paddle (EP) together. |
2 | INAP | Channel A Positive Analog Input |
3 | INAN | Channel A Negative Analog Input |
6 | COMA | Channel A Common-Mode Voltage I/O. |
7 | REFAP | Channel A Positive Reference I/O. Channel A conversion range is ±2/3 × (VREFAP - VREFAN). |
8 | REFAN | Channel A Negative Reference I/O. Channel A conversion range is ±2/3 × (VREFAP - VREFAN). |
10 | REFBN | Channel B Negative Reference I/O. Channel B conversion range is ±2/3 × (VREFBP - VREFBN). |
11 | REFBP | Channel B Positive Reference I/O. Channel B conversion range is ±2/3 × (VREFBP - VREFBN). |
12 | COMB | Channel B Common-Mode Voltage I/O |
15 | INBN | Channel B Negative Analog Input |
16 | INBP | Channel B Positive Analog Input |
18 | DIFFCLK/active-low SECLK | Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock input drives. DIFFCLK/active-low SECLK = GND: Selects single-ended clock input drive. DIFFCLK/active-low SECLK = OVDD: Selects differential clock input drive. |
19 | CLKN | Negative Clock Input. In differential clock input mode (DIFFCLK/active-low SECLK = OVDD or VDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/active-low SECLK = GND), apply the clock signal to CLKP and tie CLKN to GND. |
20 | CLKP | Positive Clock Input. In differential clock input mode (DIFFCLK/active-low SECLK = OVDD or VDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/active-low SECLK = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. |
21 | DIV2 | Divide-by-Two Clock Divider Digital Control Input |
22 | DIV4 | Divide-by-Four Clock Divider Digital Control Input |
23-26, 61, 62, 63 | VDD | Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Connect all VDD pins to the same potential. |
27, 43, 60 | OVDD | Output Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. |
28, 29, 45, 46 | N.C. | No Connect |
30 | D0B | Channel B CMOS Digital Output, Bit 0 (LSB) |
31 | D1B | Channel B CMOS Digital Output, Bit 1 |
32 | D2B | Channel B CMOS Digital Output, Bit 2 |
33 | D3B | Channel B CMOS Digital Output, Bit 3 |
34 | D4B | Channel B CMOS Digital Output, Bit 4 |
35 | D5B | Channel B CMOS Digital Output, Bit 5 |
36 | D6B | Channel B CMOS Digital Output, Bit 6 |
37 | D7B | Channel B CMOS Digital Output, Bit 7 |
38 | D8B | Channel B CMOS Digital Output, Bit 8 |
39 | D9B | Channel B CMOS Digital Output, Bit 9 |
40 | D10B | Channel B CMOS Digital Output, Bit 10 |
41 | D13B | Channel B CMOS Digital Output, Bit 11 (MSB) |
42 | DORB | Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog input voltage is out of range. DORB = 1: Digital outputs exceed full-scale range. DORB = 0: Digital outputs are within full-scale range. |
44 | DAV | Data Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The evaluation kit utilizes DAV to latch data into external back-end digital logic. |
47 | D0A | Channel A CMOS Digital Output, Bit 0 (LSB) |
48 | D1A | Channel A CMOS Digital Output, Bit 1 |
49 | D2A | Channel A CMOS Digital Output, Bit 2 |
50 | D3A | Channel A CMOS Digital Output, Bit 3 |
51 | D4A | Channel A CMOS Digital Output, Bit 4 |
52 | D5A | Channel A CMOS Digital Output, Bit 5 |
53 | D6A | Channel A CMOS Digital Output, Bit 6 |
54 | D7A | Channel A CMOS Digital Output, Bit 7 |
55 | D8A | Channel A CMOS Digital Output, Bit 8 |
56 | D9A | Channel A CMOS Digital Output, Bit 9 |
57 | D10A | Channel A CMOS Digital Output, Bit 10 |
58 | D13A | Channel A CMOS Digital Output, Bit 11 (MSB) |
59 | DORA | Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog input voltage is out of range. DORA = 1: Digital outputs exceed full-scale range. DORA = 0: Digital outputs are within full-scale range. |
64 | G/active-low T | Output Format Select Digital Input.
G/active-low T = GND: Two's complement output format selected. G/active-low T = OVDD: Gray code output format selected. |
65 | PD | Power Down Digital Input.
PD = GND: ADCs are fully operational. PD = OVDD: ADCs are powered down. |
66 | SHREF | Shared Reference Digital Input. SHREF = VDD: Shared Reference Enabled SHREF = GND: Shared Reference Disabled When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP equals VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. |
67 | REFOUT | Internal Reference Voltage Output. The REFOUT output voltage is 2.048V. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF capacitor. |
68 | REFIN | Single-Ended Reference Analog Input. For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference voltage to REFIN. For unbuffered external reference operation, connect REFIN to GND. In this mode REF_P, REF_N, and COM_ are high impedance inputs that accept the external reference voltages. |
- | EP | Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified dynamic performance. |