アプリケーションノート 3326

PWM Sets Output of LCD/LED Driver


要約: The digital, pulse-width-modulation (PWM) output available from many microprocessors is based on an internal 8- or 16-bit counter and features a programmable duty cycle. It is suitable for adjusting the output of an LCD driver, a negative-voltage LED driver, or a current-controlled LED driver.

This design idea appeared in the May 27, 2004 issue of Electronic Design magazine.

The digital, pulse-width-modulation (PWM) output available from many microprocessors is based on an internal 8- or 16-bit counter and features a programmable duty cycle. It is suitable for adjusting the output of an LCD driver (Figure 1), a negative-voltage LED driver (Figure 2), or a current-controlled LED driver (Figure 3).

Figure 1. LCD Driver with positive output voltage.
Figure 1. LCD Driver with positive output voltage.

Figure 2. LCD driver with negative output voltage.
Figure 2. LCD driver with negative output voltage.

Figure 3. Current-controlled LED driver.
Figure 3. Current-controlled LED driver.

The circuit consists simply of a PWM source, capacitor C, and resistors RD and RW. For CMOS outputs, you calculate the open-circuit output voltage as:

Equation 1.

where D is the PWM duty cycle and VDD is the logic supply voltage. The control circuit's output impedance is the sum of resistor values RW and RD:

Equation 2.

For the circuit of Figure 1, the output voltage (VOUT) is a function of the PWM average voltage (VCONT):

Equation 3.

where VREF is the reference voltage at the feedback input.

Bear in mind that the initial charge on filter capacitor C produces a turn-on transient. The capacitor forms a time constant with RCONT, which causes the output to initialize at a voltage higher than that intended. You can minimize this overshoot by scaling the value of RD as high as possible with respect to R1 and R2. As an alternative, the µP can disable the LCD until the PWM voltage stabilizes.

For Figure 2, the output voltage (VOUT) is a function of the PWM average voltage (VCONT):

Equation 4.

where VREF is the reference voltage at the feedback input.

For Figure 3, the output current (IOUT) is a function of the PWM average voltage (VCONT):

Equation 5.

where VREF is the reference voltage at the SET output and K is the current-scaling factor.

RD isolates the capacitor from the feedback loop in these PWM-adjustment methods. Assuming a stable voltage at the feedback point, the following equation defines the lowpass filter's cutoff frequency:

Equation 6.

where R = RW   RD. If RD >> RW, R ≈ RW. To minimize ripple voltage at the output, you should set the cutoff frequency at least two decades below the PWM frequency.

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APP 3326:
アプリケーションノート 3326,AN3326, AN 3326, APP3326, Appnote3326, Appnote 3326