DDR Memory-Termination Supply
The circuit of Figure 1 provides the termination voltage for both 2.5V and 1.8V memory systems, and delivers up to 6A. U1 includes a step-down controller and two linear-regulator controllers, and operates with input voltages from 4.5V to 28V. Its fixed 200kHz PWM controller maintains the output voltage by sourcing and sinking current. Maximum sink current equals the maximum source current, though the sink current has no current limit. When sinking current, the device returns some current to the input supply.
Figure 1. This circuit generates the termination voltage for DDR synchronous DRAMs.
To implement the tracking function, one of U1's extra linear-regulator controllers is configured as an inverting amplifier. This amplifier compares VDD/2 (created by R11 and R12) with VREF from U1, and generates an error signal that is applied via R6 to U1's FB pin, thereby forcing VOUT to track VDD/2. A 10mA load (R10) is required to bias the inverting amplifier for accurate tracking. VOUT can track VDD/2 for VDD in the range 1V to 4V.