DS1077L EconOscillator Architecture and Online Interactive Frequency Calculator
Block Diagram and Theory of OperationThe DS1077L 3V EconOscillator is comprised of five major blocks (Figure 1): an internal master squarewave oscillator, dual programmable prescalers, a single divider chain, gated output drivers, and a set of EEPROM configuration registers that are accessible via a 2-wire bus.
Figure 1. Dual Synchronous Outputs From 4kHz to 66.6MHz.
Internal Master Squarewave OscillatorThe master oscillator used in the DS1077L is a CMOS oscillator with compensation circuitry to eliminate most frequency variation over voltage and temperature. Four standard master frequency options are available: 40MHz, 50MHz, 60MHz, and 66.66MHz. These frequencies are calibrated at the factory and cannot be changed by the end user. In reality, the master oscillator can be factory calibrated to any frequency between 40MHz and 66.66MHz and special frequencies are available in volume quantities on request. Frequencies faster than 66.66MHz are in development at the time of the publication of this document.
Dual Programmable PrescalersThe output of the master oscillator is fed directly to two independent prescalers. These can be programmed by the user to provide an initial divide-by of the master frequency of 1, 2, 4, or 8. The prescaler settings are stored in EEPROM memory that is accessible to the end user via a 2-wire interface. These registers can be preset before installation (for fixed-frequency applications) or can be changed by a microprocessor via the 2-wire interface during operation.
The output of the first prescaler is fed directly to a gated output buffer. The second prescaler is fed into a 1-to-1025 divider chain.
Divider ChainThe 1-to-1025 divider chain receives the prescaled clock from the second prescaler and divides the clock signal down further. The division value can be programmed to any value between 1 and 1025. The divider chain settings are stored in EEPROM memory that is accessible via a 2-wire interface. These can be preset before installation into the application (for fixed-frequency applications) or can be interfaced to a microprocessor for dynamic frequency changes. The output of the divider is applied directly to a gated output buffer.
Gated Output DriversTwo gated output buffers receive the clock signal from the first prescaler and the divider chain, respectively. The status of these buffers is determined by the values of EEPROM in the EEPROM block. These gates can be turned off and on either via the 2-wire interface via the EEPROM registers or the DS1077L can be configured so that the input status of the two control pins determine the status of the outputs. The control inputs may also be configured to put the DS1077L into a powerdown mode. Output gate switching and powerdown are configured to occur only when the clock output is low. This guarantees that only full clock pulses are generated.
EEPROM Configuration RegistersEEPROM configuration registers store all configuration information. These are accessible via a 2-wire interface and may be preprogrammed before installation for fixed-frequency applications or may be controlled by a processor in applications where dynamic frequency changes or configuration changes are necessary.
For more detailed information on the DS1077L refer to the data sheet: DS1077L.