キーワード: Noopto flyback, synchronous flyback converter, peak current mode controller
関連製品 


How to Design a NoOpto Flyback Converter with SecondarySide Synchronous Rectification

Using a flyback converter for low and mediumpower applications is the preferred design choice due to the flyback converter’s simplicity and low cost. However, in isolated applications, the use of optocoupler or auxiliary winding for voltage feedback across the isolation boundary increases the number of components, and design complexity. The MAX17690, a noopto flyback controller, eliminates the optocoupler or auxiliary winding, and achieves ±5% output voltage regulation over line, load, and temperature variations.
In low output voltage and high output current applications, the diode on the secondary side of the flyback converter dissipates a significant amount of power; this power loss reduces the converter’s efficiency. The MAX17606, a secondaryside synchronous MOSFET driver, helps in replacing the secondary diode with a MOSFET. This improves the efficiency and simplifies thermal management.
This application note provides the stepbystep procedure for designing the different components of the MAX17690 + MAX17606based synchronous flyback design.
The following specification is selected to demonstrate the design calculations for the MAX17690 and the MAX17606based flyback converter. Figure 1 shows the typical application circuit for this application.
Figure 1. Application circuit.
Input voltage range  18V to 36V 
Output voltage  5V 
Maximum load current  1A 
Steadystate output voltage ripple  1% of output voltage 
Use the V_{INmin} and V_{INmax} from the selected specifications in the below equations to calculate the maximum duty cycle, D_{max}.
where:
V_{IN min} is the minimum input voltage in volts.
V_{IN max} is the maximum input voltage in volts.
D_{max} is the maximum operating duty cycle. If the calculated duty cycle is > 0.65, then choose D_{max} to be 0.65p.u.
For the present application, the switching frequency is selected as 150kHz. The R_{RT} is calculated for the selected f_{SW}.
Ω
Ω
A standard resistor of 33.2kΩ is selected.
The MAX17690 and the MAX17606 are specifically designed for the isolated flyback converters operating in Discontinuous Conduction Mode (DCM) or Border Conduction Mode (BCM). Use the below equations to select the transformer magnetizing inductance (L_{MAG}) for DCM operation.
For the present design L_{MAG} is selected to be 46.4uH, and the allowable tolerance on the L_{MAG} is ±10%. For the selected f_{sw} and the L_{MAG}, recalculate the D_{max} using the equations below:
=0.5p.u
The MAX17606 programs the turnoff trip point and decides the instant at which the secondary MOSFET is turned off. Due to the variation on the turnoff point, the secondary MOSFET conduction time changes. To guarantee the DCM operation of the converter for the variations on the turnoff threshold, magnetizing inductance (±10%), and the switching frequency (±6%), select the turnsratio (K) based on the below equations:
=0.177
For the present design, K is chosen as 0.18 ±1%.For the selected L_{MAG} and f_{SW}, the primary peak current is calculated using the equation below:
=1.28A
The threshold voltage of the peak currentlimit comparator is set at 100mV (typ) and 90mV (min). With the expected tolerance of ±10% on the L_{MAG} and the ±6% on the f_{SW}, to deliver the fullload power in all operating conditions, use the equations given below to calculate the currentsense resistor (R_{CS}) value.
= 62.5mΩ
A standard resistor of 62.5mΩ ±1% is selected.
The values of the resistordivider can be selected so that the EN/UVLO pin voltage exceeds the 1.215V (typ) turnon threshold at the desired input bus voltage (V_{START}). The same resistordivider can be modified with an additional resistor (R_{OVI}) to implement input overvoltage(V_{OVI}) protection in addition to the EN/UVLO functionality, as shown in Figure 1. When the voltage at the OVI pin exceeds 1.215V (typ), the device stops switching. With the preselected value of 10kΩ for R_{OVI}:
For the present application V_{START} and V_{OVI} are selected to be 17.5V and 36.2V.
A standard resistor of 280kΩ is selected.
Since in this design the secondary MOSFET is always programmed to conduct at the sampling instant of the output voltage, there is no need to compensate the diode forwardvoltage temp coefficient on the primary. For details on how to select the R_{TC} resistor for the other applications, refer to the MAX17690 IC data sheet.
The R_{IN}, R_{FB}, and the R_{SET} resistors program the output voltage and sampling instant for proper sampling of the output voltage. Use the below equations to calculate these values:
,and
Use the combination of standard resistors 274kΩ and 3.74kΩ to meet the required R_{FB} value of 277.7kΩ.
= 166.6kΩ
A standard resistor of 165kΩ is selected for this application.
In practice, due to the drop across the secondary leakage inductance of the transformer, the measured output voltage can deviate from the target output voltage. Use the below equations to readjust the output voltage to the desired value:
For the desired softstart time(t_{SS} = 10ms), the SS capacitor is selected using:
= 50nF
The softstart capacitor selected is 47nF for the present design.
The resistor connected between the VCM pin and SGND is used to scale the commonmode voltage of internal circuits within the operating range. Follow the below steps to select the R_{VCM} resistor value for proper operation.
= 111.1
Kc  RVCM (Ω) 

640  0 
320  75k 
160  124k 
80  220k 
40  Open 
The “RCD and RC Snubber Circuit” section covers the selection of snubber components to limit the draintosource voltage to V_{DSmax} value selected in the above equation.
The RMS current in the MOSFET can be calculated using the below equation:
In the present application, the FDMS86252 part is selected as the primary MOSFET to achieve high efficiency. From the MOSFET data sheet R_{DS(ON)} value , the conduction loss in the MOSFET can be calculated using the equation given below:
For the selected MOSFET, the equation below gives another loss component, switching loss.From the MOSFET data sheet, the C_{OSS} at 100V is given as 60pF.
=50mW
It is important to verify the maximum junction temperature of the MOSFET for the calculated losses using the below equation.where TA is the ambient temperature, the R_{TH(JA)} is the MOSFET thermal resistance from junctiontoambient, and the ^{P}MOSFET is the total MOSFET losses.
In this highefficiency design, for the selected MOSFET the total losses are a very small portion of output power, and its junction temperature is within the limits.
Use the below equation to calculate the IC driver losses for the selected MOSFET:
For the secondary MOSFET, the RMS current equation is given below:
For the stable operation of MAX17690 + MAX17606based designs over the entire operating conditions, it is recommended to select the R_{DS(ON)} of the secondary MOSFET such that the voltage across the MOSFET (at room temperature) is greater than the 100mV when the peak secondary current is flowing through the MOSFET.
In the present application, STL51N3LLH5 is selected as the secondary MOSFET.
The losses in the secondary MOSFET can be calculated using the loss equations provided in the primary MOSFET selection section and the maxim junction temperature can be verified to be within limits.
Use the following equations to calculate the snubber components:
where
The voltage rating of the snubber diode is:The RC component values are selected to be 60.4kΩ, 2.2nF.
Figure 2. Waveforms with RCD clamp.
Figure 3. RC and RCD clamp circuitry.
The RCD clamp only limits the maximum voltage stress on the primary MOSFET, but the ringing due to interaction between Llk and Cpar on the drain node is not damped. Because the MAX17690 uses the drain voltage information to sample the output voltage, it is important to damp this ringing within 350ns from the NDRV falling. In designs where this ringing is dominant, an RC snubber placed across the transformer primary winding damps this ringing. Use the following steps for designing an effective RC snubber:
1.5 to 2 x the
The R_{c} and C_{c} values are selected to be 47Ω and 220pF.
, where R_{TOFF} is in kΩ and t_{R} is in ns.
Figure 4. Secondary waveforms during synchronous MOSFET conduction.where:
L_{stray} is the MOSFET package lead inductance (see Table 2 for lead inductance of various packages).
V_{trip}: V_{trip} should be selected as 0mV (corresponds to zero secondary current instant) for f_{sw} ≤ 100kHz and 6mV for f_{sw} > 100kHz. This ensures the proper output voltage sampling and stable operation of the MAX17690 + MAX17606based design.
Figure 5. Equivalent circuit of the MAX17606.
S.No  Package  Stray inductance (nH) 

1  DFET  0.5 
2  MLP  1.8 
3  SO8, PowerPAK^{®}  1.8 
4  DPAK  2.7 
5  D2PAK  5.2 
In practice, due to delay from the comparator circuit and MOSFET turnoff time (t_{OFF}, given in the MOSFET data sheet), the R_{DRN} equation given above does not predict the exact turnoff instant. The equation given below includes these delays and determines the turnoff instant:
where:
, t_{DELAY} can be calculated using Table 3.
S.No  (mV/μs)  t_{DELAY}(ns) 

1  100.00  41 
2  66.67  45 
3  44.44  47 
4  29.63  53 
5  19.75  56 
6  13.17  63 
7  8.78  65 
8  5.85  80 
For the present design:
mV
= 2.47kΩ
A standard resistor of 2.49kΩ is selected to be the DRN resistor.
The MAX17690 offers a hiccup scheme that protects and reduces power dissipation in the circuit under output shortcircuit conditions. One occurrence of the runaway current limit, or output voltage less than 70% of regulated voltage, would trigger a hiccup mode that protects the converter by immediately suspending the switching for the period of 16,384 clock cycles. The threshold voltage of the runaway current limit comparator is set at 120mV (typ).
The MAX17690 samples the output voltage feedback when the primary MOSFET is turned off and energy stored during the “ON time” is being delivered to the secondary. Therefore, it is mandatory to switch the external MOSFET to sample the reflected output voltage. Due to the default switching, a minimum amount energy is delivered to the output capacitor under noload conditions. This small minimum load can easily be provided on the output by connecting a fixed resistor. In the absence of a minimum load, or a load less than the “minimum load,” the output voltage rises to higher values. To protect for this condition, a Zener diode of appropriate breakdown voltage rating can be installed on the output. Care should be taken to ensure that the Zener breakdown voltage is outside the output voltage envelope in both steadystate and transient conditions.
Under ideal circuit working conditions, the MAX17690 is designed to regulate the output voltage with 1% of fullload rated current on the output. With nonidealities, in most of the designs the current required to regulate the output voltage is less than 2% of the fullload rated current.
Note: Refer to the MAX17690 IC data sheet for more information.
A Zener diode with a Zener breakdown of 10% to 15% higher than the output voltage can serve as a minimum load if preloading is not acceptable. For a 5V output voltage, the Zener breakdown (V_{ZenerBR}) is selected to be 5.6V. The maximum power dissipation in the Zener diode at noload is calculated as:
where I_{minload} is the minimum load required.
In the present design, the 2% of fullload current is 20mA.
For the present design, a 5.6V, 0.5W MMSZ5232B Zener is selected. The resistor in series with the Zener is calculated based on the Zener breakdown voltage and the desired noload output voltage.
For the present design, the output voltage at absolute no load is set at 6V.
A standard resistor of 22Ω is selected.
The power dissipation in this resistor is given by:
Considering a 2% ripple on the minimum supply voltage, the input capacitance is:
=3.3μF
Two 2.2μF, 100V 1210 capacitors have been used in the present design considering the DCbiasing.
From the DCbias characteristics, the 100μF, 6.3V 1210 capacitor offers 43mF at 5V. Hence, two 100μF, 6.3V 1210 capacitors are selected for the present design.
The output voltage ripple is determined by the bulk capacitance and ESR (R_{ESR}) of the output capacitor. When using ceramic capacitors, the ESR ripple can be neglected in most of the cases. For the highripple current aluminum capacitor, the capacitance calculation begins with the maximum acceptable ripple voltage and how this ripple should be divided between the ESR step and the ripple offered by the bulk capacitance.
For a 1% contribution to the total ripple voltage, the ESR of the output capacitor should be:
For a 1% contribution to the total ripple voltage, the bulk capacitance should be:
Load pole ==740.1Hz
R_{z} = 4.39kΩ
A standard resistor of 4.3kΩ is selected.
A standard capacitor of 47nF is selected.
== 493pF
A standard capacitor of 470pF is selected.
Note: When the ESR zero of the output capacitor is significant, the compensator pole capacitor (C_{p}) should be selected to cancel the ESR zero.
Design & Simulate MAX17690 using EESim
関連製品  
MAX17606  2次側同期整流MOSFETドライバ、フライバックコンバータ用 
無料 
MAX17690  60V、フォトカプラ不要の絶縁型フライバックコントローラ 
無料 
MAX17690EVKITA  MAX17690の評価キット 
次のステップ  

EEMail配信の登録申し込みをして、興味のある分野の最新ドキュメントに関する自動通知を受け取る。 
ダウンロード  ダウンロード、PDFフォーマット (630.5kB) 
© Dec 11, 2017, Maxim Integrated Products, Inc. 
APP 6394: Dec 11, 2017
アプリケーションノート6394, AN6394, AN 6394, APP6394, Appnote6394, Appnote 6394 