The MAX3420E is a USB full-speed (12Mbps) peripheral controller with a built-in transceiver and a USB serial interface engine (SIE) that handles the low-level USB signaling details.
No. The MAX3420E is designed to interface easily to any microprocessor, DSP, or ASIC. This makes it possible to add USB to any system without switching processors or tool sets.
The MAX3420E is available in two packages. The 32-pin TQFP (7mm x 7mm body size) is good for prototyping and short production runs because it has package leads. The 24-pin TQFN package (5mm x 5mm body size, pads underneath the package) is ideal for high-volume compact devices.
The MAX3420E supports USB full-speed (12Mbps) operation as a peripheral.
The MAX3420E is compliant with the USB 2.0 specification as it applies to full-speed operation.
The MAX3420E contains four endpoints:
With these endpoints, it is possible to build USB peripherals that support popular USB class drivers, such as a Human Interface Device (HID), Mass Storage, Picture Transfer Protocol (PTP), and Printer.
ISOCHRONOUS transfers require fast interfaces and large buffers, neither of which is consistent with the MAX3420E design goals (a low-cost part with an SPI interface that can run at any speed). Most applications that seem to require ISOCHRONOUS bandwidth can actually be handled with BULK or INTERRUPT transfers. This is because most of the ISOCHRONOUS bandwidth available to a USB device in a system is also typically available for BULK/INT transfers.
Absolutely. In fact, the MAX3420E has features specifically intended to support self-powered applications. For example, in a self-powered application the peripheral needs to know when the device is plugged into a powered USB port. The MAX3420E's VBCOMP (VBUScomparator) pin is connected to VBUS, and routed to an internal comparator that provides an interrupt request at plug-in (VBUSIRQ) and another interrupt request at disconnect (NOVBUSIRQ). As another example for the MAX3420E, a bit called VBGATE (VBUS gate) can be set to automatically disconnect the D+ pullup resistor whenever VBUS is detected to be off. This is a required USB specification.
Yes. In a bus-powered application, a 3.3V voltage regulator is connected to the USB connector's VBUS pin. Whenever the peripheral is plugged into USB, the chip and the SPI master driving it are powered. So there is no need to connect the MAX3420's VBCOMP pin to VBUS. In this case, the VBCOMP input can be used as an extra general-purpose input. Care must be taken to ensure that input signals to this pin meet the threshold requirements noted in the MAX3420 Electrical Characteristics table.
The MAX3420E requires a VCC supply of 3.3V. Bus-powered peripherals need a 3.3V regulator to convert the power available on the VBUSpin (4.4V to 5.25V) to 3.3V. In addition, the MAX3420E requires an external crystal (parallel resonant, 12MHz ±0.25%) with load capacitors from each pin to ground, and two series resistors (33Ω, 1%) between the D+/D- outputs, and the USB "B" connector.
The MAX6349TL is ideal. It supplies 150mA at 3.3V, and contains a power-on-reset (POR) circuit which can be connected directly to the MAX3420E RES# pin. A good external POR circuit is important to have in a hot-plugged design such as a USB peripheral.
The MAX3420E has a switchable internal 1500Ω pullup resistor between its D+ pin and VCC. The CONNECT bit operates this switch. This switch allows a bus- powered peripheral to delay connection to USB until it finishes initialization. It also allows a self-powered peripheral to remove VCC from the pullup resistor in the absence of VBUS, as required by the USB Specification.
The microprocessor connects to the MAX3420E by implementing an SPI master, using 3, 4, or 5 wires. Some microcontrollers include hardware SPI, but many do not. In this latter case, it is easy to implement an SPI master by bit-banging general-purpose IO pins.
The minimum SPI interface consists of three wires: SS# (Slave Select), SCLK (Serial Clock), and MISO (configured for bidirectional MISO/MOSI data). Since this interface does not use the INT pin, the controlling microprocessor would need to poll two interrupt-request registers to determine when the MAX3420E requires service.
By setting a control bit (FDUPSPI, full-duplex SPI), the MOSI and MISO data appear on separate pins, providing a 4-wire interface. Finally, an INT (interrupt out) pin can be connected to a processor's interrupt system.
The SPI mode is usually expressed in the form (x,y) where one variable is the clock polarity, CPOL, and the other is the clock phase, CPHA. The MAX3420E operates in modes (0,0) or (1,1) without requiring a mode bit. The only difference between these modes is the inactive SCLK level: low for (0,0), high for (1,1). There are two basic requirements for running the MAX3420E SPI interface:
Be careful with these modes—some microprocessor data sheets do not adhere to the (0,0) and (1,1) convention. It is best to verify the above two points when setting a clock mode. Also see the MAX3420E data sheet and MAX3420E Programming Guide for SPI example waveforms.
No. The MAX3420E contains internal level shifters. A VL pin powers the internal logic and serves as the logic reference voltage for the SPI and IO pin signals. For a 2.5V interface, connect your 2.5V supply to the VL pin. The VL pin can actually operate with a range of voltages from 1.7V to 3.6V. If the controller uses 3.3V, tie VL to VCC.
The INT pin goes active whenever the MAX3420E requires service. During USB peripheral operation, this includes the arrival of SETUP, IN or OUT packets, plus bus events like bus reset, suspend, and resume. Using this pin in a system reduces the SPI traffic since the interrupt request bits do not need to be polled over the SPI interface.
The MAX3420E supports both interrupt types, using a control bit called INTLEVEL. Setting INTLEVEL=1 makes the INT output pin open-drain, active-low for wired-OR applications. This mode requires an external pullup resistor to VL. Setting INTLEVEL=0 (the default value) makes the INT pin edge-active with a push-pull output driver. In edge mode, a second bit called POSINT sets the edge polarity to positive or negative.
With VL of 2.5V or greater, the SCLK signal can be as high as 26MHz. For lower VL values, the data sheet shows how much to derate the SCLK maximum frequency.
No. This clock can be held high or low indefinitely. Also, the MAX3420E ignores SCLK transitions while SS# is high.
The MAX3420E has four general-purpose outputs (GPOUT3-0) and four general-purpose input pins (GPIN3-0) that are set and read using the IOPINS register, R20. This replaces the microcontroller pins used to implement the SPI interface, and provides additional ones.
No. The GPIN pins are internally pulled up (typical value of 20kΩ) to VL.
Yes. The MAX3420E outputs have enough drive current to drive optocoupler LEDs through series resistors. Consult the data sheet for exact drive specs. The output buffers were designed with opto-isolation in mind, since the MAX3420E SPI interface is uniquely suited to electrically isolating USB.
No. The VBCOMP pin does not power anything in the MAX3420E. It goes only to an internal comparator to detect the presence of VBUS.
The MAX3420E has a set of 21 registers that are accessed by its slave SPI interface. The SPI master first sends a command byte that sets the register address and direction, and then transfers one or more data bytes.
As a peripheral, the MAX3420E device needs only to respond to requests from the host (usually a PC).
When you have data ready to send to the host, load an IN FIFO, then write the byte count register for the particular endpoint. Since the IN FIFOs are 64 bytes in length, up to 64 bytes can be loaded at a time. When finished loading the data, write the IN endpoint BYTECOUNT register with the number of bytes loaded into the IN FIFO. Writing the byte count register "arms" the endpoint for USB transfer. The MAX3420E does the rest. The next IN request to its device address and the armed endpoint sends the FIFO data to the host.
The MAX3420E takes care of this. It automatically answers an IN request to an "unarmed" IN FIFO with a NAK (Negative Acknowledge) handshake. This handshake instructs the USB host that the endpoint is busy, and that the host should try later with another IN request.
The MAX3420E provides interrupt request bits for the IN endpoints called IN3BAVIRQ, IN2BAVIRQ, and IN0BAVIRQ, where "BAV" indicates "Buffer Available". The MAX3420E logic sets an IN endpoint BAVIRQ bit after a device reset, or when IN FIFO data has been successfully transferred and acknowledged by the host. At power-on, the BAVIRQ bits are set to indicate that the IN FIFOS are initially available for loading. These are the only register bits that are set to 1 by a reset—all the rest are set to 0.
No. The MAX3420E manages this for you. If the MAX3420E receives an error condition back from the host, it automatically resends the same data when the host retries the IN transfer. The MAX3420E also automatically handles other error checking such as data toggles. Some possible USB errors (such as a user unplugging the cable in the middle of a data transfer) need to be handled by firmware.
When the host sends OUT data, the MAX3420E stores the bytes in an OUT endpoint FIFO. After the transfer is complete and verified to be error-free, the MAX3420E asserts a "DAV" (Data Available) interrupt request bit for the particular endpoint. This alerts the SPI controller to read the FIFO bytes. The SPI controller first reads an OUT FIFO byte-count register to determine how many bytes in the 64 byte FIFO are valid. It then reads that number of bytes by repeated reads to the OUTFIFO register. Finally, the SPI controller clears the OUT DAV IRQ bit (by writing 1 to it) to "rearm" the endpoint for another OUT transfer.
Interrupt transfers are programmed identically to BULK transfers. They differ only in how they are described in the device descriptors sent back to the host during enumeration.
The USB host uses a CONTROL transfer to send a SETUP packet to the MAX3420E along with eight bytes that serve as a USB "op-code". The MAX3420E stores these bytes in an 8-byte FIFO, and then asserts a Setup Data Available interrupt request. The SPI master responds by reading the eight SETUP bytes at register address R4 (SUDFIFO), interpreting the USB request from these bytes, and taking the appropriate action. When finished servicing the request, the SPI master sets a bit called ACKSTAT (ACK from acknowledge, STAT from STATUS stage) to tell the MAX3420E to acknowledge the status stage of the CONTROL transfer.
No. The MAX3420E handles these toggles automatically during USB transfers. The only time firmware might need to intervene is when the host sets a new configuration in a multiconfiguration design (these are rare). The MAX3420E has register bits to clear the endpoint toggles for this purpose.
It may seem backwards at first, but it is the most efficient way to clear a register bit. To service a typical interrupt request, the SPI master reads an interrupt request register (either USBIRQ or EPIRQ), and checks using various bit masks to determine the source of the interrupt. For example, to test for the SUDAVIRQ interrupt request, firmware would read R11 (EPIRQ) and AND the result with 00100000 (the SUDAVIRQ bit is in the bit 5 position). Typically a program will equate a label like bmSUDAV with 0010000. Once the IRQ bit is detected to be a 1, the firmware can simply write the mask value back to the register (SUDAVIRQ = bmSUDAV) and only the desired bit is cleared. IRQ bits written with a zero are unchanged.
When using the SPI full-duplex mode, the very first register access should set the FDUPSPI bit to 1 in order to correctly set up the interface for subsequent accesses.
A Windows® application talks to the PC's USB host controller through a driver. The driver may be built into Windows or it may be custom. Windows includes built-in drivers for standard device classes, such as Human Interface Devices (HID) and Mass Storage Devices. If your firmware supports one of these standard classes, your customer does not need to load a custom driver.
If you are designing a device that does not conform to one of the built-in Windows standard device classes, the end user must install a custom driver when your USB device is plugged in the first time.
You can find example C code for implementing a HID application on the Maxim website at USB Enumeration Code (and More) for the MAX3420E. This example code emulates a PC keyboard, which types a text string into any Windows application that accepts text (e.g., Notepad) whenever a pushbutton is pressed. By conforming to the standard HID class, the application runs without a custom Windows driver. Regardless of your target application, most of this example code is USB 'boilerplate' that can be used as a starting point for your code.
There are two alternatives:
Microsoft has announced a general-purpose BULK driver for USB in the upcoming "Vista" version of Windows.
USB serial bridge chips connect to a PC using its USB port, but appear as a virtual COM port to the application running on the PC . A custom driver, supplied by the chip vendor, is required to do this COM-USB transformation. A Windows application that talks to a serial (COM) port (e.g., HyperTerminal) can be used to talk to an USB-connected device using this method.
The advantage of this approach is that no enumeration firmware or host driver is required. The disadvantages are in performance, flexibility, and support:
The disadvantages are that firmware is required for the MAX3420E controller and that Maxim does not supply a custom Windows driver. Instead, Maxim supplies example firmware to illustrate how to conform to a standard Windows device class (HID), and thereby to use a built-in Windows driver.
The advantages to the MAX3420E approach are performance, flexibility and support.
Yes. The read-only register R18 contains the revision number.
Refer to the MAX3420E Product Folder for the latest data sheet and errata.
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