The key is to find out how much capacitance exists between XTAL1 and XTAL2 on your board and to get a crystal which is designed to oscillate at that capacitance. For example, the MAX1470 evkit presents a capacitance of about 5pF between XTAL1 and XTAL2. Therefore if a crystal designed to oscillate with a 5pF load is used, no additional capacitance is needed and you can "short" the series capacitors. If a crystal designed to operate at a higher load capacitance is used, the crystal will oscillate at a higher frequency, and additional capacitance is needed to pull the crystal to the correct frequency. As a rule, parallel capacitance is needed to pull the crystal lower, while series is needed to pull it higher. Ultimately, the best test is to monitor the IF frequency (after the filter) on a spectrum analyzer. The deviation of the IF from 10.7MHz will determine how much capacitance needs to be added, keeping in mind that the added capacitance will affect "cold" start-up time and the shutdown current. Please refer to the application note: "How to Choose a Quartz Crystal Oscillator for the MAX1470 Superheterodyne Receiver."
The design of the control loop is such that it could accommodate such a high ESR. A high ESR will increase current consumption (slightly) and will increase "cold" start-up time (not an issue with the MAX1470 since the oscillator circuit is running continuously even in shutdown mode) Having said all that, in the long term a lower ESR value would be preferable.
The 250µsec start-up time is from the positive edge of the PWRDN signal to valid data, with approximately 100msec of power cycling. This time is unaffected by minimum sensitivity and includes the time it takes for the PLL to lock. The PLL lock time is actually more in the 100µsec range. It should be noted that the start up time from "cold" could be up to 10ms. This is due to the crystal start up time and any pulling capacitors that it may have. This is the main reason why the PWRDN feature keeps the crystal running.
It is true that this time doesn't include the time for the baseband circuitry to slice the data. The time for the baseband circuitry depends on the time constants and also on the power cycling frequency. When the MAX1470 is in PWRDN mode, the data slicer inputs are disconnected from R1 and C4 to prevent the cap from discharging. If wake-up times are spaced too far apart, then the cap could discharge, adding to the start-up time.
As far as the shutdown pin, there is no internal pull-up or pull-down. Therefore, it would be recommended to include one externally to control it in high impedance cases. Keep in mind to use a large value, so as to reduce current draw.
The way the typical circuit is setup, it is more suitable for no DC offset signals. That isn't to say that the IC wouldn't work with varying DC offset. The slicing threshold may have to be setup differently.
Unfortunately this is a normal phenomena. You can force an offset on the slicer by adding a pull-up resistor on pin 20. However, this will reduce your sensitivity. Another solution is to add a preamble to the transmitter so the receiver can distinguish between noise and signal. Your micro can sample the receiver output periodically and check for a valid signal.
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