Reliability Monitor Program


Maxim monitors the reliability of devices representative of those shipped from production to ensure that failure rates are met on a continuing basis. Through the Reliability Monitor Program (RMP), the reliability of key wafer fab and assembly processes are monitored under accelerated conditions. Sample sizes vary but are typically 200+ devices per family divided between a variety of environmental stresses. The results from the RMP are updated in this report quarterly.  

All failures from the RMP are verified then analyzed for cause of failure. The results of this analysis are used to establish corrective actions to eliminate the failure mechanisms found.

The PROCESS RELIABILITY Section includes historical data through the previous quarter for IC products and Operating Life Stresses. Data is organized by design technology.

The PACKAGE RELIABILITY section summarizes the assembly/package stresses through the previous quarter and before.

Data Sheets and Application Notes are in Adobe Acrobat format. If you do not already have this reader installed, you can download the most current Acrobat Reader free from Adobe Systems Inc.


Preconditioning stresses are used to monitor the contribution that post assembly environment has on the reliability of devices. All preconditioning stresses are done according to J-STD-020 and are used to monitor all package types determined to be moisture sensitive. These package types, at this time, include CSBGA's, LQFP's, MCMBGA's, MQFP's, PBGA's, PLCC's, Power Cap Bases', SOIC's, SOT's, SSOP's, TQFP's, TSOC's, TSSOP's, TSOP's and µSOP . This stress consists of a bake, moisture soak, and two or three passes of convection reflow prior to splitting the lot into the various stress groups.  An ultrasound test is performed pre and post the preconditioning to look for package cracks and die surface delamination from the package.

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Operating Life

These stresses simulate typical device performance at elevated temperatures and maximum operating voltages and, then, use the relationship between temperature, voltage, and time to derate failure rates obtained under these accelerated conditions to use conditions. The chamber where devices are stressed consists of an oven capable of withstanding the temperatures used during the accelerated stressing. Devices are biased via life test boards programmed to provide dynamic exercising of the circuit. Devices are electrically tested at various read points in order to determine under these accelerated conditions how the device might perform in infant life and long term life. Devices are required to satisfy all data sheet specifications over full voltage and temperature ranges at all read points, independent of the type of stress. Operating life tests are performed on integrated circuits only. Usual conditions are 125°C, 5.5 volts or 6.0 volts, for 1000 hours.

The Arrhenius model will be used to determine the acceleration factor for failure mechanisms that are temperature accelerated. 

AfT = exp((Ea/k)*(1/Tu - 1/Ts)) = tu/ts 
AfT = Acceleration factor due to Temperature 
tu = Time at use temperature (e.g. 55°C) 
ts = Time at stress temperature (e.g. 125°C) 
k = Boltzmann's Constant (8.617 x 10-5 eV/K) 
Tu = Temperature at Use (K) 
Ts = Temperature at Stress (K) 
Ea = Activation Energy (e.g. 0.7 ev) 

The activation energy of the failure mechanism is derived from either internal studies or industry accepted standards, or activation energy of 0.7ev will be used whenever actual failure mechanisms or their activation energies are unknown.  This is a conservative industry standard. All deratings will be done from the stress ambient temperature to the use ambient temperature. 

An exponential model will be used to determine the acceleration factor for failure mechanisms, which are voltage accelerated. 

AfV = exp(B*(Vs - Vu)) 
AfV = Acceleration factor due to Voltage 
Vs = Stress Voltage (e.g. 7.0 volts) 
Vu = Maximum Operating Voltage (e.g. 5.5 volts) 
B = Constant related to failure mechanism type (e.g. 1.0, 2.4, 2.7, etc.)

The Constant, B, related to the failure mechanism is derived from either internal studies or industry accepted standards, or a B of zero will be used whenever actual failure mechanisms or their B are unknown. All deratings will be done from the stress voltage to the maximum operating voltage. Failure rate data from the operating life test is reported using a Chi-Squared statistical model at the 60% or 90% confidence level (Cf).

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Storage Life

The purpose of this stress is to accelerate aging of product under storage conditions and is used for Telecom, EPROM, & EEPROM integrated circuits. Typical conditions are 150°C for 1000 hours with no bias applied. The stress chamber is an oven capable of withstanding the high temperatures of the storage condition. Some battery backed modules are initially subjected to storage life as a preconditioning stress (48 hours), but under a reduced temperature of 85°C due to the thermal limitations of the lithium battery. Other battery backed products are subjected to storage life for 1000 hours at temperatures of 70°C or 85°C. Devices are electrically tested at various read points in order to evaluate the performance of the product over time.

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Temperature Cycle

The object of this stress is to simulate the conditions of temperature change due to power-up/power-down sequences which devices are normally subjected to under use conditions. This stress will reveal weaknesses in design related to mismatch of thermal characteristics in the package materials and in the die to package relationships. Typical conditions vary with product. For integrated circuits, -55°C to +125°C (no bias) for 1000 cycles, is the usual stress. Thermal transition and soak times conform to MIL-STD-883, Method 1010, Condition B. For modules or other battery backed products the stress range is reduced to 0°C to +70°C or -40°C to +85°C (no bias). Devices are electrically tested at each read point to full data sheet specifications.

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Temp Humidity Bias

The purpose of this stress is to determine the performance of products when subjected to a humid, high temperature environment. Standard, industry accepted, stress tests have been developed which are designed to simulate field conditions over the life time of the product. These standard stresses are 130°C / 85% relative humidity for 96 hours (HAST) or 85°C / 85% relative humidity for 1000 hours. Both stresses are performed with maximum alternating bias, in this case, 3.5/5.5 and 0.0 volts, which provides an opportunity for electrochemical corrosion. Devices are configured for lowest power dissipation to reduce internal heating and subsequent reduction in internal humidity. This stress examines the integrity of the encapsulated device and the quality of the surface passivation to prevent corrosion on integrated circuits. The stress is used for both modules and integrated circuits. Other battery backed products are subjected to moisture soak consisting of 60°C and 90% relative humidity without external bias. Autoclave testing consists of 121°C and 2 Atmospheres of pressure without bias for 96 hours and is performed on integrated circuits. Devices are electrically tested at all read points.

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Write Cy/Data Ret'n

Write Cycle and Data Retention stresses are performed on EEPROM devices. Only Data Retention is performed on EPROM devices. The Write Cycle stress consists of alternating write zero's followed by write one's of the entire matrix. This is defined as one cycle.  The stress may be performed at 25°C, 70°C, or 85°C depending on device specifications. The number of cycles will vary and is also dependent upon device specifications but typically will be some number between 25K cycles and 50K cycles.  After the last cycle, the device is written with an alternating (checkerboard) pattern then subjected a data retention test with a storage life condition of 150°C for 1000 hours.  Functionality and data patterns are verified after the each readpoint of this stress.

EPROM devices are not subjected to the Write Cycle stress but are written with a checkerboard pattern followed by the the Data Retention test described above.

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Package Integrity

The purpose of the package integrity testing is to verify the incoming quality of our assembly suppliers by performing package tests to currently qualified specifications. Physical dimensions and Solderability of modules, and Ultrasound of surface mount packages are performed and reported as part of the RMP. Lead integrity, Solderability, X-ray views, X-ray fluorescence, and external visual tests are performed on integrated circuits by Incoming Quality Control on a weekly monitor basis. These IQC monitors include all package types per assembly sites for product received each week. 

Ultrasound testing is a sensitive technique that can delineate package voids and internal interface separations and cracks. All of this can be done nondestructively. No internal crack nor die surface delamination is allowed in this inspection.

Solderability is tested per MIL-STD-883, Method 2003. All leads are dipped on a sample size of three units, then 24 leads on the three devices are inspected. Type R Flux is used. Accept criteria is 95% coverage. For the Modules, type RMA Flux is used and acceptance criteria is 90% coverage. 

Lead Integrity is tested to JEDEC JESD22 - B105. Twenty-four leads are tested on a sample size of six units. A 15° bend is used for Plastic DIP and SOIC. 

Radiography (X-ray) is performed per MIL-STD-883, Method 2012. Top and side views of x-rays are recorded on film. 

X-ray fluorescence is performed to verify plating thickness and composition. 

External visual is performed per an internal DSC specification (27-03510-000) in order to verify the correct marking and external package integrity.

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