5.1µA 1-Cell Fuel Gauge with ModelGauge m5 EZ and Optional High-Side Current Sensing

Industry's Lowest IQ Fuel Gauge with ModelGauge m5 EZ Eliminates Battery Characterization

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General Description

The MAX17260 is an ultra-low power fuel gauge IC which implements the Maxim ModelGauge™ m5 algorithm. The IC monitors a single-cell battery pack and supports both high-side and low-side current sensing.

The ModelGauge m5 EZ algorithm makes fuel gauge implementation easy by eliminating battery characterization requirements and simplifying host software interaction. The algorithm provides tolerance against battery diversity for most lithium batteries and applications. The algorithm combines the short-term accuracy and linearity of a coulomb counter with the long-term stability of a voltage-based fuel gauge, along with temperature compensation to provide industry-leading fuel gauge accuracy. The IC automatically compensates for cell-aging, temperature, discharge rate, and provides accurate state-of-charge (SOC) in percentage (%) and remaining capacity in milliampere-hours (mAh) over a wide range of operating conditions.  As the battery approaches the critical region near empty, the algorithm invokes a special correction mechanism that eliminates any error. The IC provides accurate estimation of time-to-empty and time-to-full and provides three methods for reporting the age of the battery: reduction in capacity, increase in battery resistance, and cycle odometer.

The IC provides precision measurements of current, voltage, and temperature. The temperature of the battery pack is measured using an internal temperature sensor or external thermistor. A 2-wire I2C interface provides access to data and control registers. The IC is available in tiny lead-free 0.4mm pitch, 1.5mm x 1.5mm, 9-pin WLP package and 3mm x 3mm, 14-pin TDFN package.

Simple Fuel-Gauge Circuit Diagram
Page-1 Sheet.501 Sheet.502 TH TH Sheet.504 Sheet.505 Sheet.506 Resistor-v.85 Sheet.508 Sheet.509 Sheet.510 Sheet.511 MAX17260 MAX17260 Sheet.512 Sheet.514 Sheet.515 Sheet.516 Sheet.517 Sheet.518 Sheet.519 Sheet.520 Sheet.521 0.1µF 0.1µF Sheet.525 10kΩ NTC 10k NTC Sheet.526 Sheet.527 Sheet.528 Sheet.529 Sheet.530 Sheet.532 Sheet.536 Sheet.542 Sheet.543 SCL SCL Sheet.544 SDA SDA Sheet.545 ALRT ALRT Sheet.546 Sheet.547 CSPL (TDFN) CSPL (TDFN) Sheet.552 Sheet.553 BATT BATT Sheet.554 CSN CSN Resistor-v.880 Sheet.558 Sheet.559 Sheet.560 Sheet.561 Sheet.562 Sheet.563 REG REG Sheet.564 Sheet.567 Sheet.568 Sheet.569 Sheet.570 Sheet.571 Sheet.578 SYSPWR SYSPWR Sheet.579 SYSGND SYSGND Sheet.580 Sheet.581 Sheet.582 Sheet.586 Sheet.587 Sheet.588 Sheet.589 Sheet.590 Sheet.591 Sheet.592 Sheet.594 Sheet.595 Sheet.596 Sheet.597 Sheet.598 Sheet.599 Sheet.600 Sheet.603 Sheet.604 Sheet.605 Sheet.606 RSENSE RSENSE Sheet.608 PROTECTION CIRCUIT PROTECTION CIRCUIT Sheet.614 EP (TDFN) EP (TDFN) Sheet.615 Sheet.616 Center drag circle.942 Sheet.618 Sheet.619 Sheet.620 Sheet.621 Sheet.622 Sheet.623 Resistor-v.949 Sheet.625 Sheet.626 Sheet.631 Sheet.638 CSN CSN Sheet.639 Sheet.640 Sheet.641 Sheet.642 Sheet.643 Sheet.645 RSENSE RSENSE Sheet.646 OPTIONAL HIGH-SIDE SENSING OPTIONAL HIGH-SIDE SENSING Sheet.647 Sheet.650 CSPH CSPH Sheet.653 GND GND Sheet.537 0.47µF 0.47µF
Benefits and Features
  • ModelGauge m5 EZ
    • No Characterization Required for EZ Performance
    • Robust Against Battery Variation
    • Eliminates Error Near Empty Voltage
    • Eliminates Coulomb-Counter Drift
    • Compensates for Age, Current, and Temperature
    • Does Not Require Empty, Full, or Idle States
  • Low 5.1μA Operating Current
  • Accurate Current Sensing
    • High-Side or Low-Side Sensing Option
  • Wide Sense Resistor Range: 1mΩ to 1000mΩ
  • Trace Sensing with Temperature Compensation
  • Supports Li+ and Variants Including LiFePO4
  • Thermistor or ±1°C Internal Temperature
  • Dynamic Power Estimates Power Capability During Discharge
  • Time-to-Empty and Time-to-Full Estimation
  • Predicts Remaining Capacity Under Theoretical Load
  • No Calibration Required
  • Alert Indicator for Voltage, SOC, Temperature, Current, and 1% SOC Change

19-100249; Rev 1; 6/18

  • Wearables, Smartwatches
  • Tablets, 2-in-1 Laptops
  • Bluetooth Headsets
  • Health and Fitness Monitors
  • Digital Still, Video, and Action Cameras
  • Medical Devices
  • Handheld Computers and Terminals
  • Wireless Speakers
  • Home and Building Automation, Sensors
  • Portable Game Players
  • Toys
Absolute Maximum Ratings
  • BATT to GND-0.3V to +6V
  • ALRT to GND-0.3V to +17V
  • REG to GND-0.3V to +2.2V
  • TH to GND-0.3 V to VBATT + 0.3 V
  • CSN to GND-0.3V to VBATT + 0.3V
  • CSPH to GNDVBATT - 0.3V to VBATT + 0.3V
  • CSPL to GND-0.3V to +0.3V
  • SDA, SCL to GND-0.3V to +6V
  • Operating Temperature Range-40°C to +85°C
  • Junction Temperature+150°C
  • Storage Temperature Range-55°C to +125°C
  • Soldering Temperature (reflow)+260°C
  • Continuous Source Current for TH1mA
  • Continuous Sink Current for SDA, ALRT20mA
  • Lead Temperature (soldering 10s)+300ºC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Information
Package Code W91G1+2
Outline Number 21-100168
Land Pattern Number Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 83.98​ºC/W
Junction to Case (θJC) NA

Package Code T1433+2C
Outline Number 21-0137
Land Pattern Number 90-0063
Thermal Resistance, Single-Layer Board:
Junction to Ambient (θJA) 54​ºC/W
Junction to Case (θJC) 8​ºC/W
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 41​ºC/W
Junction to Case (θJC) 8​ºC/W

For the latest package outline information and land patterns (footprints), go to Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to


Electrical Characteristics
(VBATT = 2.3V to 4.9V, TA = -40ºC to +85ºC, typical value for TA is +25ºC. Limits are 100% tested at TA = +25°C. The operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.)
Electrical Characteristics (continued)

(VBATT = 2.3V to 4.9V, TA = -40ºC to +85ºC, typical value for TA is +25ºC. Limits are 100% tested at TA = +25°C. The operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Specifications marked "GBD" are guaranteed by design and not production tested.)

Supply Voltage VBATT (Note 1) 2.3 4.9 V
Shutdown Supply Current IDD0 T≤ +50ºC 0.5 0.9 μA
Hibernate Supply Current IDD1 T≤ +50ºC, average current 5.1 12 μA
Active Supply Current IDD2 T≤ +50ºC, average current not including thermistor measurement current 15 30 μA
Regulation Voltage VREG 1.8 V
Startup Voltage VBATTSU 3 V
BATT Measurement Error VGERR T= +25ºC -7.5 +7.5 mV
-40ºC ≤ T≤ +85ºC -20 +20
BATT Measurement Resolution VLSB 78.125 μV
BATT Measurement Range VFS 2.3 4.9 V
Current Measurement Offset Error IOERR Long-term average without load current ±1.5 μV
Current Measurement Error IGERR -1 +1 % of Reading
Current Measurement Resolution ILSB 1.5625 μV
Current Measurement Range IFS ±51.2 mV
Internal Temperature Measurement Error TIGERR -40ºC ≤ T≤ +85ºC ±1 ºC
Internal Temperature Measurement Resolution TILSB 0.00391 ºC
External Thermistance Resistance REXT10 Config.R100 = 0 10
REXT100 Config.R100 = 1 100
Output Drive Low, ALRT, SDA VOL IOL = 4mA, VBATT = 2.3V 0.4 V
Input Logic High, ALRT, SCL, SDA VIH 1.5 V
Input Logic Low, ALRT, SCL, SDA VIL 0.5 V
Battery-Detach Detection Threshold VDET Measured as a fraction of VBATT on TH rising 91 96.2 99 %
Battery-Detach Detection Threshold Hysteresis VDET-HYS Measured as a fraction of VBATT on TH falling 1 %
Battery-Detach Comparator Delay tTOFF TH step from 70% to 100% of VBATT (Alrtp = 0, EnAIN = 1, FTHRM = 1) 100 μs
Leakage Current, CSN, ALRT ILEAK VALRT < 15V -1 +1 μA
Input Pulldown Current IPD VSDA = 0.4V, VSCL = 0.4V 0.05 0.2 0.4 μA
SCL Clock Frequency fSCL (Note 2) 0 400 kHz
Bus Free Time Between a STOP and START Condition tBUF 1.3 μs
Hold Time (Repeated) START Condition tHD:STA (Note 3) 0.6 μs
Low Period of SCL Clock tLOW 1.3 μs
High Period of SCL Clock tHIGH 0.6 μs
Setup Time for a Repeated START Condition tSU:STA 0.6 μs
Data Hold Time tHD:DAT (Note 4, Note 5) 0 0.9 μs
Data Setup Time tSU:DAT (Note 4) 100 ns
Rise Time of Both SDA and SCL Signals tR 5 300 ns
Fall Time of Both SDA and SCL Signals tF 5 300 ns
Setup Time for STOP Condition tSU:STO 0.6 μs
Spike Pulse Width Suppressed by Input Filter tSP (Note 6) 50 ns
Capacitive Load for Each Bus Line CB (Note 7) 400 pF
SCL, SDA Input Capacitance CBIN 6 pF
Time-Base Accuracy tERR T= +25°C -1 +1 %
TH Precharge Time tPRE 8.48 ms
Note 1:  All voltages are referenced to GND.
Note 2:  Timing must be fast enough to prevent the IC from entering shutdown mode due to bus low for a period greater than the shutdown timer setting.
Note 3:  fSCL must meet the minimum clock low time plus the rise/fall times.
Note 4:  The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 5:  This device internally provides a hold time of at least 100ns for the SDA signal (refer to the minimum VIH of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 6:  Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 7:  Crepresents total capacitance of one bus line in pF.
Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)