MAXQ1850

DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography

Low Pin-Count Cryptographic Microcontroller with Advanced Physical Security


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Description

DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.

The DeepCover Secure Microcontroller (MAXQ1850) is a low-power, 32-bit RISC device designed for electronic commerce, banking, and data security systems. It combines high-performance, single-cycle processing, sophisticated tamper-detection technology, and advanced cryptographic hardware to provide industry-leading data security and secret key protection.

Physical security mechanisms include environmental sensors that detect out of range voltage or temperature conditions, responding with rapid zeroization of critical data. Four self-destruct inputs are provided for additional tamper response. An internal shield over the silicon provides protection from microprobe attacks. A high-speed internal ring oscillator is provided to thwart attacks that rely on controlling the clock rate of the chip. To protect data, the MAXQ1850 integrates several high-speed, analysis-resistant encryption engines. Algorithms supported in hardware include AES (128-, 192-, and 256-bit), DES, triple DES (2-key and 3-key), ECDSA (160-, 192-, and 256-bit keys), DSA, RSA (up to 2048 bits), SHA-1, SHA-224, and SHA-256. The advanced security features of the MAXQ1850 are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria certifications.

The MAXQ1850 includes 256KB of flash memory and 8KB of secure, battery-backed data SRAM. Several communication protocols are supported with hardware engines, including ISO 7816 for smart card applications, USB (slave interface with four end-point buffers), an RS-232 universal synchronous/asynchronous receiver-transmitter (USART), an SPI interface (master or slave mode support), and up to 16 general-purpose I/O pins. Other peripherals supported on the MAXQ1850 include a true hardware random-number generator (RNG), a real-time clock (RTC), a programmable watchdog timer, and flexible 16-bit timers that support capture, compare, and pulse-width modulation (PWM) operations.

Note: Designers must have following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation.

Key Features

  • High-Performance 32-Bit MAXQ30 RISC Core
  • DC to 16MHz Operation, Approaching 1MIPS per MHz
  • Single 3.3V Supply Enables Low Power/Flexible Interfacing
  • 65MHz Cryptography Engine Execution to Reduce Processing Time
  • On-Chip 2x/4x Clock Multiplier
  • 5V Tolerant I/O
  • Up to 16 General-Purpose I/O Pins
  • 33 Instructions, Most Single Cycle
  • Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement
  • Virtually Unlimited Software Stack
  • 16-Bit Instruction Word, 32-Bit Internal Data Bus
  • 16 x 32-Bit Accumulators
  • CRC-16, CRC-32 generator
  • Security Features
    • Tamper Sensors Instantaneously "Zeroize" Internal Keys and User Data When:
      • Out-of-Range Temperature/Voltage Detected
      • User-Defined Self-Destruct Inputs (SDIx) Activated
    • Internal Cryptographic Hardware Includes:
      • DES Engine Supporting Single DES and 2/3-Key 3DES Operations
      • AES Engine supporting 128-, 192- and 256-bit Key Length
      • Public-Key Cryptographic Accelerator for ECDSA (160-, 192-, and 256-Key Strength)
      • Public-Key Cryptographic Accelerator for DSA and RSA (1024- and 2048-Key Strength)
      • Hardware Hash Engine Supports SHA-1, SHA-224, SHA-256
    • Unresettable True-Time Clock Self-Imposes Expiration Dates and Date/Timestamping
  • Memory Features
    • Secure Memory Management Unit
    • 256KB of Internal Flash Program Memory
    • 8KB Internal Battery-Backed NV SRAM
  • Peripheral Features
    • USB Device Controller with Four Endpoint Buffers
    • ISO 7816 UART with FIFO with Two Physically Separate Communication Buses
    • One General Purpose UART
    • Two 16-bit Timers
  • Power Management Features
  • In-System Programming Through Debug Port or Serial Port
  • Ultra-Low Battery Leakage to Support NV RAM and Security Sensors (130nA)

Applications/Uses

  • ATM Keyboards
  • Certificate Authentication
  • Electronic Commerce
  • Electronic Signature Generator
  • EMV® Banking
  • Pay-per-Play
  • PCI Terminals
  • PIN Pads
  • Secure Access Control
  • Secure Data Storage
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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Belle Isle 2020
05/29/2020 - 05/31/2020, Detroit, MI
2020 Detroit Grand Prix - Chevrolet Detroit Grand Prix presented by Lear Fast Facts The Chevrolet Detroit Grand Prix presented by Lear was hosted on Belle Isle, May 29 - 30 2020. The event featured the cars of the NTT IndyCar Series, the IMSA WeatherTech SportsCar Championship and the Trans Am Series presented by Pirelli. The weekend is collectively referred to as the Chevrolet Detroit Grand Prix presented by Lear and it once again featured the Chevrolet Dual in Detroit IndyCar doubleheader.

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