DeepCover Secure Microcontroller for Magnetic Card Reading

Single-Chip Secure Magnetic Stripe Reader Solution with Hardware Cryptography and Secure Key Storage

Please check latest availability status for a specific part variant.


DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.

The DeepCover Secure Microcontroller (MAXQ1740) integrates a triple-track magnetic stripe reader interface, an I²C interface, two SPI interfaces, and one universal synchronous/asynchronous receiver-transmitter (USART) interface. Security features include an AES encryption engine, a true hardware random-number generator, voltage-attack sensors, and a self-destruct input pin. A single-cycle 16-bit RISC MAXQ® CPU powers the device. It provides a high level of security for the magnetic stripe reader by placing an ultra-secure microcontroller with high-speed hardware encryption inside the magnetic card reader head.

The device provides 16KB of flash memory, 1KB of fast-wipe nonvolatile SRAM (NV SRAM), and 128 bytes of data NV SRAM that instantaneously zeroizes its contents when a tamper is detected. The 128 bytes can be used as data RAM or working RAM for the AES. The fast-wipe feature ensures that any data in the 1KB of memory is destroyed before any application software can access it. Factory programming of a unique 64-bit serial number, and/or customer secret key(s), is available upon request. The microcontroller runs within a wide 1.7V to 3.6V operating range. User-application firmware interfaces with the triple-track magnetic stripe interface. Reference software supports the reading of cards adhering to ISO 7811, ISO 7812, and ISO 7813. Source code to the reference software is available so applications can make adjustments for custom card formats.

An ultra-low-power stop mode provides the ultimate in low-power performance. In this mode, only a minimum amount of circuitry is powered to support detection of self-destruct events. When the main power supply is present and the microcontroller is in stop mode, the device has the option of exiting stop mode when stimulated by general-purpose port pins or the serial interfaces.

Key Features

  • Core Functionality
    • High-Performance, Low-Power, 16-Bit MAXQ20C RISC Core
    • 6MHz Internal Oscillator (±10%)
    • Up to 12MHz External Crystal Supported
    • 1.7V to 3.6V Operating Voltage
    • 1-Wire® Interface for Debugger and Flash Programming
    • Optimized for C-Compiler
  • Security
    • AES Hardware Accelerators
    • Hardware True Random-Number Generator
    • Self-Destruct Input for Tamper Detection
    • Permanent Loader Lockout Option
    • Code Scrambling
  • Memory
    • 16KB Flash Memory
      • 512 Bytes Memory Page Sectors
      • 1000 Erase/Write Cycles per Sector
    • 1152 Bytes Fast-Wipe NV SRAM, 128 Bytes Usable by Cryptographic Engine
    • 6KB Utility ROM with User-Callable Routines
  • I/O and Peripherals
    • Triple-Track Magnetic Stripe Head Interface
    • Two SPI Communication Ports
    • USART Communication Port
    • Two 16-Bit Timers
    • I²C Communication Port
    • Up to 16 General-Purpose I/O Pins
    • Up to 8 External Interrupt Pins
  • Low Power Consumption
    • 3μA Current in Lowest Power Stop Mode
    • 3.75mA (typ) at 6MHz, 0.8mA (typ) at 1MHz
    • Divided System Clock Modes Available
  • Additional Peripherals
    • On-Chip Power-On/Power-Fail Reset
    • Supply Overvoltage Detection
    • Programmable Watchdog Timer
    • Wake-Up Timer


  • ATM/POS Terminals
  • Physical Security/Building Access

Technical Documents

App Note 5094 Improve Magnetic Card Reading in the Presence of Noise

Quality and Environmental Data

Product Reliability Reports: MAXQ1740.pdf 
Lead-Free Package Tin (Sn) Whisker Reports
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

Quality Management System >
Environmental Management System >


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