High-Speed Secure Microcontroller

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Designed to meet the most stringent security validations of FIPS 140 and Common Criteria, the DS5240 is ideal for high-security designs required in the banking and financial industry.

The DS5240 is a high-speed 8051 compatible microcontroller with expanded addressing features. This device offers extended memory addressing of up to 4MB program and 4MB data and a 1kB stack (part of 5kB total SRAM) for high-level language support. The nonmultiplexed byte-wide bus leaves four 8-bit ports and one 6-bit port for user I/O application.

Security features include on-chip sensors to detect out-of-range environmental conditions to generate tamper response, fast write SRAM for rapid zeroing secure information for threat response, a Modulo Arithmetic Accelerator (MAA) using words up to 4096-bits in length for calculations including Public Key Infrastructure (PKI). The DS5240 provides a user Data Encryption Standard (DES) engine that provide both single and triple-DES cryptographic operations.

Advanced features of the DS5240 include 4 clock-per-machine cycle architecture, single cycle instructions execute in 160ns, dual data pointers with independent increment and decrement, automatic data pointer selection, programmable length MOVX instructions for fast and slow external devices, power management, and watchdog timer.

Complete Technical Information
Due to the strong cryptographic features of the DS5240, full disclosure of confidential details are available from the microcontroller technical support group. For a list of available documentation for the DS5240, go to Complete Technical Information.

Key Features

  • Security Features
    • Designed to Meet the Physical Security Requirements of FIPS140 and Common Criteria Certifications
    • Fine-Line, Top-Level Metal Pattern Detects Intrusion of the Chip’s Cryptographic Boundary
    • Additional On-Chip Sensors Detect Out-of-Range Environmental Conditions That Generate a Tamper Response
    • Equipment Enclosure Can Be Monitored by Tamper Response Inputs for Added Protection
    • Fast Write SRAM Technology Causes Rapid "Zeroization" of Secure Information as a Tamper Response
    • Eavesdropping on the External Memory Bus Prevented by Single or Triple-DES Encryption of the Programs
    • Internal Chip Clock Isolated from External System Clock by Phase-Locked Loop
    • Asynchronous Internal Ring Oscillator Provides Clock for Arithmetic Operations
    • Resources Inside Cryptographic Boundary Include:
      • Modulo Arithmetic Accelerator (MAA) for Up to 4096-Bit (e.g., PKI)
      • DES and 112-Bit Key Triple-DES Engines Available for Secret Key Cryptography
      • Random Number Generator
      • Memory Management Unit and 1kB Cache
      • Firmware Bootstrap Loader Resides in a 16kB Factory-Programmed ROM
  • 8051-Compatible with Expanded Addressing
    • Linear Address Space Directly Accesses Up to 8MB of External Memory
    • Dedicated Memory and Parallel I/O Bus Saves Port Pins
    • Four 8-Bit Ports, One 6-Bit Port
  • Advanced Features
    • CRC-16/32 Generator Provides Strong Error Detection of Memory Contents
    • True-Time Clock with Alarm Interrupt and Wakeup
    • 5kB Internal SRAM with 1kB That Can Be Allocated to a Stack for High-Level Language Support
    • Programmable Length MOVX Instructions Allow a Combination of Fast and Slow Devices
    • On-Chip Power Detection/Selection Circuits Provide Power-Up/Down Processor Reset and Early-Warning Power-Fail Interrupt
    • Watchdog Timer
  • Proven 4-Clock/Machine Cycle Architecture
    • Single-Cycle Instruction Executes in 160ns
    • Runs Up to 25MHz Clock Rates
    • Dual Data Pointers Can Increment or Decrement Independently
    • Automatic Data Pointer Selection Available
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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