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10/100 Fast Ethernet MicroPHY

MicroPHY is the Smallest Ethernet PHY in the Industry

Product Details

Key Features

Simplified Block Diagram

Technical Docs

Data Sheet 10/100 Fast Ethernet MicroPHY Oct 13, 2010

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Sampling:
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Key Features

  • Low Power and Flexible Power-Supply Management
    • Power-Down/Save and Transmitter Disable
    • Power-Off State Dissipation < 20mW
  • Single 3.3V Supply Operation with Low Power Dissipation
    • Optimized Low Power Design
  • HP Auto-MDI/MDI-X Automatic Cable Crossover Correction
  • Fully Integrated 802.3u Fast Ethernet Transceiver
  • Commercial and Industrial Temperature Ranges

Applications/Uses

  • Digital Video Recorders/Players
  • High Definition 1080P/1080i DTVs
  • High-Performance Satellite, Cable, and IPTV Set-Top Boxes
  • IP-PVR and Video Distribution Systems
  • Multimedia Residential Gateways

Description

Housed in a 32-pin, 5mm x 5mm QFN package, the MicroPHY® is the smallest Fast Ethernet PHY available that provides a full 802.3 media independent interface (MII) to the system media controller.

The 78Q2123/2133 MicroPHYs are designed to meet the growing demands of nontraditional networked applications such as game consoles, set-top boxes, and digital TVs. The tiny size gives designers an edge when board space is at a premium, and its single 3.3V supply requirements eliminate the need for 1.8V regulators or additional voltage conversion capacitors.

The integrated HP Auto MDI/MDI-X function, a must for consumer electronic applications, automatically compensates for crossover cable problems eliminating one of the most common items for consumer help lines.

The MicroPHY’s full MII allows the device to easily interface to any 802.3-compliant MAC. The MicroPHY offers all the essential pins for embedded applications including reset pin, power-down pin, programmable LEDs and more. On-chip regulators masterfully achieve supply-noise isolation among the various blocks while reducing the number of off-chip supply filtering components. A semidigital architecture and digital clock recovery unit are used in the receiver to maximize circuit noise immunity.

The MicroPHY includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured autonegotiation functions. The transmitter includes an on-chip pulse-shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling through 1:1 isolation transformers without the need for external filtering.

Simplified Block Diagram

 

Technical Docs

Data Sheet 10/100 Fast Ethernet MicroPHY Oct 13, 2010

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .

Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.