Top

Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop

Product Details

Key Features

Parametric specs for High-Speed Interconnect (Differential Signaling)
Signal Type (Rx) ECL
LVECL
LVPECL
PECL
Signal Type (Tx) ECL
LVECL
LVPECL
PECL
Functions D Flip-Flop
# Rx 2
# Tx 2
Propagation Delay (ps) (max) 490
VSUPPLY (V) 5
Package/Pins SOIC (N)/8
UMAX/8
Budgetary
Price (See Notes)
5.41
View Less

Simplified Block Diagram

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .

Parameters

Parametric specs for High-Speed Interconnect (Differential Signaling)
Signal Type (Rx) ECL
LVECL
LVPECL
PECL
Signal Type (Tx) ECL
LVECL
LVPECL
PECL
Functions D Flip-Flop
# Rx 2
# Tx 2
Propagation Delay (ps) (max) 490
VSUPPLY (V) 5
Package/Pins SOIC (N)/8
UMAX/8
Budgetary
Price (See Notes)
5.41

Key Features

  • 3.0GHz Guaranteed Operating Clock Frequency
  • 0.2psRMS Added Random Jitter
  • 328ps Typical Propagation Delay
  • PECL Operation from VCC = 2.25V to 5.5V with VEE = 0V
  • ECL Operation from VEE = -2.25V to -5.5V with VCC = 0V
  • Input Safety Clamps Ensure Output Stability when Inputs are Open or at VEE
  • ±2kV ESD Protection (Human Body Model)
  • Applications/Uses

    • Automated Test Equipment (ATE)
    • Central Office Telecom Equipment
    • DLCs
    • DSLAM
    • Precision Clock and Data Distribution
    • Wireless Base Stations

    Description

    The MAX9381 differential data, differential clock D flip-flop is pin compatible with the ON Semiconductor MC100EP52, with the added benefit of a wider supply-voltage range from 2.25V to 5.5V and 25% lower supply current. Data enters the master part of the flip-flop when the clock is low and is transferred to the outputs upon a positive transition of the clock. Interchanging the clock inputs allows the part to be used as a negative edge-triggered device. The MAX9381 utilizes input clamping circuits that ensure the stability of the outputs when the inputs are left open or at VEE.

    The MAX9381 is offered in an 8-pin SO package and the smaller 8-pin µMAX package.

    Simplified Block Diagram

    MAX9381: Functional Diagram MAX9381: Functional Diagram Zoom icon

    Technical Docs

    Support & Training

    Search our knowledge base for answers to your technical questions.

    Filtered Search

    Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .