27-Bit, 5MHz to 42MHz DC-Balanced LVDS Deserializers
Fully Integrated, Single-Link Deserializer for Digital Video Applications
DescriptionThe MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial-data rate. The MAX9248/MAX9250 pair with the MAX9247 serializer to form a complete digital video transmission system. For operating frequencies less than 35MHz, the MAX9248/MAX9250 can also pair with the MAX9217 serializer.
The MAX9248 features spread-spectrum capability, allowing output data and clock to spread over a specified frequency range to reduce EMI. The data and clock outputs are programmable for a spectrum spread of ±4% or ±2%. The MAX9250 features output enable input control to allow data busing.
Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9248/MAX9250 feature a selectable rising or falling output latch edge.
ESD tolerance is specified for ISO 10605 with ±10kV Contact Discharge and ±30kV Air-Gap Discharge.
The MAX9248/MAX9250 operate from a +3.3V ±10% core supply and feature a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. These devices are available in a 48-lead LQFP package and are specified from -40°C to +85°C or -40°C to +105°C.
- Programmable ±4% or ±2% Spread-Spectrum Output for Reduced EMI (MAX9248)
- Proprietary Data Decoding for DC Balance and Reduced EMI
- Control Data Deserialized During Video Blanking
- Five Control Data Inputs are Single-Bit-Error Tolerant
- Output Transition Time is Scaled to Operating Frequency for Reduced EMI
- Staggered Output Switching Reduces EMI
- Output Enable Allows Busing of Outputs (MAX9250)
- Clock Pulse Stretch on Lock
- Wide ±2% Reference Clock Tolerance
- Synchronizes to MAX9247 Serializer Without External Control
- ISO 10605 and IEC 61000-4-2 Level 4 ESD Protection
- Separate Output Supply Allows Interface to 1.8V to 3.3V Logic
- +3.3V Core Power Supply
- Space-Saving LQFP Package
- -40°C to +85°C and -40°C to +105°C Operating Temperature Ranges
- In-Vehicle Entertainment Systems
- LCD Displays
- Navigation System Displays
- Video Cameras
Technical DocumentsApp Note 4211 EMI-/EMC-Ready SerDes—Basic Test Strategies and Guidelines
App Note 4099 Evaluate Serializer-Deserializer (SerDes) Performance by Creating Eye Pattern Templates
App Note 4020 Working with MAX9217/MAX9218/MAX9247/MAX9248/MAX9250 Evaluation Boards
App Note 4007 Robust, Fail-Safe Biasing Circuit for AC-Coupled Multidrop LVDS Bus
App Note 3964 Enabling Test Modes on the MAX9247
App Note 3806 Performance Test for a Serializer and Deserializer Pair: MAX9247 and MAX9218
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|App Note||4211||EMI-/EMC-Ready SerDes—Basic Test Strategies and Guidelines|
|App Note||4099||Evaluate Serializer-Deserializer (SerDes) Performance by Creating Eye Pattern Templates|
|App Note||4020||Working with MAX9217/MAX9218/MAX9247/MAX9248/MAX9250 Evaluation Boards|
|App Note||4007||Robust, Fail-Safe Biasing Circuit for AC-Coupled Multidrop LVDS Bus|
|App Note||3964||Enabling Test Modes on the MAX9247|
|App Note||3806||Performance Test for a Serializer and Deserializer Pair: MAX9247 and MAX9218|