The DS28CN01 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the Federal Information Publications (FIPS) 180-1/180-2 and ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The memory is organized as four pages of 32 bytes each. Data copy-protection and EPROM emulation features are supported for each memory page. Each DS28CN01 has a guaranteed unique factory-programmed 64-bit registration number. Communication with the DS28CN01 is accomplished through an industry standard I²C- and SMBus™-compatible interface. The SMBus timeout feature resets the device's interface if a bus-timeout fault condition is detected.
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