DeepCover Security Manager with 1KB Secure Memory and Programmable Tamper Hierarchy

Tamper-Detection Hierarchy with On-Chip Nonimprinting Memory Safeguard Critical Data

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DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.

The DeepCover Security Manager (DS3644) is a secure supervisor with 1024 bytes of SRAM for the secure storage of sensitive data and the physical tamper-sensing response functions required in cryptographic processors and data security equipment.

One of the DS3644's primary features is the on-chip nonimprinting memory, consisting of eight 128-byte banks incorporating a high-speed, direct-wired clearing function. The 1KB memory is constantly complemented in the background to prevent memory imprinting of data. The DS3644 architecture allows the user to clear selective banks of the memory based upon specified tamper events. In the event of a qualified tamper event, the desired bank(s) of memory are rapidly cleared and a negative bias can be applied to erase external memory.

The DS3644 includes a seconds counter, watchdog timer, CPU supervisor, nonvolatile (NV) SRAM controller, and on-chip temperature sensor. In the event of a primary power failure, an external battery source is automatically switched in to keep the memory, time, and tamper-detection circuitry active. The DS3644 provides low-leakage, tamper-detection inputs for interface to external sensors, interlocks, and antitamper meshes. The DS3644 also invokes a tamper event on absolute temperature, if the temperature rate-of-change exceeds programmed limits, or if the crystal oscillator frequency falls outside a specified window. The tamper event is latched and timestamped for fault-recovery purposes.

Access to the timer, tamper monitoring, memory, and device configuration is conducted through an I²C-compatible interface. The DS3644 is assembled in a Pb-free, 7mm x 7mm x 0.8mm CSBGA package.

Key Features

  • Memory
    • 1024-Byte Nonimprinting Memory with High-Speed Erase
    • 64 Bytes General-Purpose RAM (Not Cleared)
    • External SRAM Control and Optional Tamper-Event Erasure
    • Segmented Tamper-Detection Memory Hierarchy with Programmable Tamper-Event Sources
  • Tamper
    • On-Chip Programmable Temperature Sensing with Proprietary Rate-of-Change (ROC) Detector
    • Two General-Purpose Tamper-Detect Logic Inputs
    • Four Uncommitted Tamper-Detect Comparator Inputs
    • Four Window Comparators with On-Chip Reference Voltage
    • Latching and Timestamping of Tamper Events
    • Crystal Oscillator Tamper Monitoring
  • Other
    • Programmable Power-Consumption Options for Very Low Standby Current
    • 64-Bit Unique Silicon Serial Number
    • On-Chip Random-Number Generator (RNG)
    • 32-Bit Seconds Counter with Watchdog Timer and Alarm Output
    • CPU Supervisor
    • I2C-Compatible Interface


  • Access-Control Security Systems
  • ATMs
  • Cryptographic Processors
  • E-Commerce Servers
  • Gaming Systems
  • Network Routers and Switches
  • Network Storage Servers
  • PIN Pads
  • Point-of-Sale Terminals
  • Secure Communications
  • Set-Top Boxes
  • Smart Card Readers
  • Software-Defined Radios

See parametric specs for Security Managers (12)

Part NumberAnalog Voltages MonitoredDigital Inputs MonitoredInternal Key Memory
Package/PinsOper. Temp.
DS3644 421024
-55 to +95

Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.
Product Reliability Reports: DS3644.pdf 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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