DS2475

DeepCover ECDSA Coprocessor with 1-Wire Master

Offloads Host ECDSA Computing and 1-Wire Line Driving from Host Processor


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Description

DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.

The DeepCover Elliptic Curve Digital Signature Algorithm (ECDSA) coprocessor with built-in 1-Wire® master (DS2475) enables the efficient implementation of public- key based authentication when combined with an ECDSA secure authenticator. Additionally, for operation with 1-Wire ECDSA authenticators, an I2C-to-1-Wire protocol conversion function relieves the system host processor from generating time-critical 1-Wire waveforms. The DS2475 interfaces directly to standard (100kHz max) or fast (400kHz max) I2C masters. When not in use, the DS2475 can be put in sleep mode where power consumption is minimal.
DS2475: Typical Application Circuit DS2475: Typical Application Circuit Enlarge+

Key Features

  • High-Speed ECDSA Engine for Public-Key Signature Verification
  • Implements NIST FIPS 186-Based ECDSA Algorithm
  • Integrated NIST FIPS 180 SHA-256 Engine for Efficient ECDSA Input Data Computation
  • 1-Wire Line Driver Supporting Both Standard and Overdrive Communication Speeds
  • Supports Power-Saving Sleep Mode (SLPZ Pin)
  • ±8kV ESD Protection on IO to GND (JESD22-A114 HBM, typ)
  • Operating Range: 3.3V ±10%, -40°C to +85°C
  • 6-Pin SOT23 Package

Applications/Uses

  • Authentication of Accessories
  • Authentication of Consumables
  • Peripheral Authentication

Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

DS28E35EVKIT: Evaluation System for the DS28E35
Product Reliability Reports: DS2475.pdf 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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