
Embedded Security Devices

Embedded Security Devices
Embedded systems need protection from malicious attacks. Add tamper detection to your system to protect sensitive data and encryption keys. Or safeguard your IP and R&D investment from cloning and unauthorized use. With Maxim’s solutions, you can easily secure your entire system.
Security manager products work with your microcontroller to protect information. Secure Authenticator ICs provide HW-based crypto-strong authentication and coprocessing. Our secure microcontrollers have built-in FIPS-certified hardware cryptographic engines that support industry-standard algorithms.
Analog ICs provide complete analog circuit functions.
Security Managers
Secure Authentication
NFC/RFID Products
Secure Microcontrollers
Featured Technical Documents
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Technical Documentation

Technical Documents
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Featured Blog
Latest Blogs
September 17, 2020
See how secure authenticators and coprocessors make it easier for you to integrate cryptography to protect your embedded designs.
September 10, 2020
Understand the threats that cryptographic systems face and how you can guard against these threats.
August 18, 2020
Learn why a hardware-based approach to cryptography provides more robust protection of IoT designs than software cryptography.
August 06, 2020
Learn how a new cryptographic coprocessor makes it easy to implement end-to-end encryption and other cybersecurity features for IoT devices.
July 02, 2020
Learn how physically unclonable function (PUF) technology works and what makes it a robust security solution for embedded systems.
June 16, 2020
Understand how cryptography algorithms, including symmetric keys and asymmetric keys, work their magic to protect designs from security threats.
June 09, 2020
Get a better understanding of how modern cryptography works, with special emphasis on asymmetric and symmetric keys.
May 07, 2020
Get up to speed on the basics of cryptography, so you can protect your IoT designs from hackers and other security threats.
April 09, 2020
Counterfeit vehicle parts are a potential safety hazard. Read this blog post to learn how secure authentication easily protects your automotive designs from security threats.
September 03, 2019
Ben Smith narrates a 30-second video that explains how ChipDNA™ physically unclonable function technology secures embedded designs.
Featured Products
MAX36210 Security Supervisor with SP800-90A/B TRNG, Tamper Detection, and Cryptography
- Low-Power Security Supervisor Enables Cost Effective Security Solution
- 1KB Battery-Backed NV SRAM with High-Speed Erase on its AES-256 Encryption Key
- 4KB Flash Data Storage
- Battery-Backed Tamper Circuit and RTC
- Low-Current Battery-Backup Operation
- Operates from Single 3.3V Supply
- Security Features Facilitate System-Level Protection
- Tamper Detection with Fast Wipe Key/Data Destruction
- Hardware Accelerators for AES (128/192/256), 3DES, RSA (1024/2048/4096), ECDSA (p256/p384/p521), SHA (1/224/256/384/512)
- True Hardware Random-Number Generator (NIST SP800-90B output and SP800-90A post process)
- Temperature, Voltage and Die Shield Sensors to Detect Attacks
- 2 Pairs of External Sensor Tamper Detects
- Time Stamp for Tamper Event
- Encrypted NV SRAM Data Transfer
- Authentication with Connected Host
- 104-Bit Unique Serial Number
- Integrated Peripherals Allows for Easy Integration into Applications
- Programmable Alarm with External Output
- CPU Supervisor
- SPI, I²C, UART Interfaces
- 4 GPIO Pins
DS28E40 Deep Cover Automotive 1-Wire Authenticator
- ECC-P256 Compute Engine
- FIPS 186 ECDSA P256 Signature and Verification
- ECDH Key Exchange for Session Key Establishment
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 198 HMAC for Bidirectional Authentication
- SHA-256 One-Time Pad Encrypted R/W of Configurable Memory Through ECDH Established Key
- One GPIO Pin with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional ECDSA Certificate Verification to Set On/Off after Multiblock Hash for Secure Boot
- TRNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip-Generated Pr/Pu Key Pairs for ECC Operations
- 6Kb of One-Time Programmable (OTP) for User Data, Keys, and Certificates
- Unique and Unalterable Factory-Programmed 64-Bit Identification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- Single-Contact, 1-Wire Interface Communication with Host at 9.09kbps and 62.5kbps
- 3.3V ±10%, -40°C to +125°C Operating Range
- ±8kV HBM ESD protection of 1-Wire IO Pin
- 10-Pin, 3mm x 4mm TDFN Package
- AEC-Q100 Grade 1
DS2488 1-Wire Dual-Port Link
- Two-Contact Solution Enables Advance TWS Features
- Small Message Exchange between a Case and Earbuds
- High-Speed 512kbps Pass-Through Mode to Transfer Files
- Earbud Battery Charger Power Delivery
- Three GPIO Pins for Optional Feature Control or State Detection
- Full Range of Capabilities for Earbud and Charging Case Detection
- Earbud 64-Bit Identification Number (ROM ID) Readable upon Insertion
- Operating Power Parasitically Derived from the 1-Wire IOA Line
- Detect when in or out of a Charging Case
- Detect a Dead Charging Case Battery
- Minimalist Dual 1-Wire Interface Reduces Cost and Complexity
- Single Dedicated Contact for Communication and Power
- Arbitrated Communication between Two Host Controllers at 90kbps
- Reads and Writes over a Wide 1.71V to 3.63V Voltage Range
- Ideal for Battery Power Consumer Applications
- Small, 1.6mm x 0.9mm x 0.33mm WLP with 0.4mm Ball Pitch
- 1.71V to 3.63V Operating Voltage Range
- High ESD Immunity of IOA Pin: ±8kV HBM (typ)
- -40°C to +85°C Operation

DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA
- Secure Coprocessor with NIST-Compliant Hardware-Based Crypto
- FIPS-180 SHA-256 MAC and FIPS-198 HMAC Hash
- FIPS-197 AES-128 with GCM
- FIPS-186 ECDSA-P256 Elliptic Curve Digital Signature/Verification
- SP800-56A ECDHE-P256 Key Exchange
- SP800-90B Compliant TRNG
- Robust Countermeasures Protect Against Security Attacks
- ChipDNA Produced Key Cryptographically Protects All Stored Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- Enables Fast Time-to-Market with Easy End Application Integration
- Fixed-Function Command Set, No Device-Level Firmware
- C-Source Demos for Examples of SW Development
- 3.6KB Flash Array for Secure Key, Certificate, and Data Storage
- High-Speed Interface for Host Microcontroller Communication
- 20MHz SPI with Mode 0 or Mode 3 Operation
- Supplemental Features Enable Easy Integration into End Applications
- Unique and Unalterable Factory-Programmed, 64-Bit Identification Number (ROM ID)
- Low-Power Operation
- 100nA Power-Down Mode
- 0.35mA Idle
- 12-Pin 3mm x 3mm TDFN

DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer
- Operate Remote I2C or SPI Devices Using Single-Contact 1-Wire Interface
- Extending I2C/SPI Communication Distance
- Reduce Six Wires (for SPI) or Four Wires (for I2C) to Two Wires
- 512-Byte Sequencer for Autonomous Operation of Attached Devices
- Two Configurable GPIO Pins for Additional Peripheral Control
- No External Power Required
- DS28E18 Parasitically Powered from 1-Wire
- I2C/SPI Peripheral Power Derived from the 1-Wire Line
- Flexible 1-Wire and I2C/SPI Master Operational Modes
- Supports Standard (11kbps) and Overdrive (90kbps) 1-Wire Communication
- 100kHz, 400kHz, and 1MHz for I2C Slaves
- Up to 2.3MHz for SPI Slaves
- Easy to Integrate
- Small, 2mm x 3mm x 0.75mm, 8-Pin TDFN Package
- -40°C to +85°C Operation
- 2.97V to 3.63V Operating Voltage Range

DS28E38 DeepCover® Secure ECDSA Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Public-Key Authentication Solution to Authenticate Peripherals
- FIPS 186-Compliant ECDSA P256 Signature for Challenge/Response Authentication
- Options for ECDSA Public/Private Key Pair Source Include ChipDNA Generated, Chip Computed, and User Installed
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 2Kbits of EEPROM for User Data, Key, Control Registers, and Certificate
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Single-Contact, 1-Wire Interface Communication with Host at 11.7kbps and 62.5kbps
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
- 2-Pad SFN Package (3.5mm x 6.5mm)

DS28C16 I²C Low-Voltage SHA-3 Authenticator
- Robust Countermeasures Protect Against Security Attacks
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- Secure Storage for Secrets
- 256 Bits of Secure EEPROM for User Data
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- I²C Communications Up to 1MHz
- Operating Range: 1.62V–3.63V, -40°C to +85°C
- 8-Pin, 2mm x 2mm TDFN-EP Package

DS2477 DeepCover Secure SHA-3 Coprocessor with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates and Manages Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Bidirectional Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 2Kb of EEPROM for User Data, Key, and Control Registers
- One Open-Drain GPIO Pin
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Large 1-Wire Block Buffer (126 bytes) for Efficient Data Transfer
- 1-Wire Standard and Overdrive Timing Communication Speeds
- I²C Communication, Up to 1MHz
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)

DS28E36 DeepCover Secure Authenticator
- ECC-256 Compute Engine
- FIPS 186 ECDSA P256 Signature and Verification
- ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 180 MAC for Secure Download/Boot Operations
- FIPS 198 HMAC for Bidirectional Authentication and Optional GPIO Control
- Two GPIO Pins with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional Set On/Off after Multiblock Hash for Secure Boot/Download
- RNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip Generated Pr/Pu Key Pairs for ECC Operations
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 8Kbits of EEPROM for User Data, Keys, and Certificates
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- Single-Contact 1-Wire Interface Communication with Host at 11.7kbps and 62.5kbps
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
MAX66240 DeepCover Secure Authenticator with ISO 15693, SHA-256, and 4Kb User EEPROM
- Dedicated Hardware-Accelerated SHA Engine
- Strong Authentication with a High Bit Count User-Programmable Secret and Input Challenge
- 4096 Bits of User EEPROM with User-Programmable R/W Protection Options Including OTP/EPROM Emulation Mode
- Unique Factory-Programmed 64-Bit Identification Number
- ISO/IEC 15693: Up to 26kbps
- ±2kV HBM ESD Protection for All Pins
DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- ECDSA Authenticated R/W of Stored Data and Counter
- Efficient Public-Key Authentication Solution to Authenticate Peripherals
- FIPS 186-Compliant ECDSA P256 Signature for Challenge/Response Authentication
- ChipDNA Generated Public/Private Key Pair.
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 2Kb of EEPROM for User Data, Key, Control Registers, and Certificate
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- I2C Communication: Up to 200kHz
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)

DS28E16 1-Wire Secure SHA-3 Authenticator
- Robust Countermeasures Protect Against Security Attacks
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- Secure Storage for Secrets
- 256 Bits of Secure EEPROM for User Data
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Advanced 1-Wire Protocol Minimizes Interface to Single Contact
- Full-Time Overdrive Communication Speed
- Internal Parasite Power Capacitor
- Operating Range: 1.71V–3.63V, -40°C to +85°C
- WLP, TDFN-EP, and SFN Packages
- ±8kV HBM ESD Protection (typ)
- 3.5µA (typ) Input Load Current
MAX32561 DeepCover Secure Arm Cortex-M3 Flash Microcontroller
- Arm Cortex M3 Processor Core Allows for Easy Integration into Applications
- 108MHz Core Operating Frequency Through PLL
- 1MB Dual-Bank Flash Memory with Cache
- 384KB System SRAM
- 8KB AES Self-Encrypted NVSRAM
- Security Features Facilitate System-Level Protection
- ISO 14443 type A/B EMV Compliant Contactless Reader with Internal Transceiver
- Secure Boot Loader with Public Key Authentication
- AES, DES and SHA Hardware Accelerators
- Modulo Arithmetic Hardware Accelerator (MAA) Supporting RSA, DSA, and ECDSA
- 9-Line Secure Keypad Controller
- Hardware True Random-Number Generator
- Die Shield with Dynamic Fault Detection
- 6 External Tamper Sensors with Independent Random Dynamic Patterns
- 256-Bit Flip-Flop-Based Battery-Backup AES Key Storage
- Temperature and Voltage Tamper Monitor
- Real-Time Clock
- Integrated Peripherals Reduce External Component Count
- Triple-Track Magnetic Stripe Head Interface
- One ISO 7816 Smart Card Interface with Integrated Transceiver (1.8V, 3V, and 5V) and One Smart Card Interface Only
- USB 2.0 Device with Internal Transceiver and Dedicated PLL
- 2 SPI Ports, 2 UART Ports, and I²C Controller
- 6 Timers, 2 with PWM Capability
- Up to 39 General-Purpose I/O Pins
- 1-Channel, 10-Bit ADC
- 4-Channel DMA Controller
- 1 SPI Execute in Place (XiP) Master
- Power Management Optimizes Battery Life and Reduces Active Power Consumption
- Single 3.3V Supply Operation*
- Integrated Battery-Backup Switch
- Clock Gating Function
- Low-Current Battery-Backup Operation
Download Data Sheet
Errata MAX32561 | MAX32561_A7_NDA_Rev1.pdf |
NDA Required. Request Full Data Sheet and Software
MAX32592 DeepCover Secure Microcontroller with ARM926EJ-S Processor Core
- High Performance CPU platform Enables Feature Rich OS
- Arm926EJ-S™ Processor Core with 16KB Data Cache and 32KB Instruction Cache
- 4KB Instruction TCM, 4KB Data TCM
- Up to 400MHz Core Operating Frequency
- Up to 200MHz Multilayer AHB Bus Matrix
- Up to 100MHz APB Bus Matrix
- 384KB System SRAM
- Flexible Clock Prescalers
- Configurable Low-Power Modes
- Security Features Facilitates System-Level Protection
- Secure Bootloader with Public Key Authentication
- 256-Bit Flip-Flop-Based Nonvolatile AES Key Storage
- 24KB AES User-Encryptable NV SRAM
- 2KB User-Programmable OTP
- AES, DES, and SHA Hardware Accelerators
- Modulo Arithmetic Hardware Accelerator (MAA) Supporting RSA, DSA, and ECDSA
- Secure Keypad Controller
- Hardware True Random Number Generator
- Die Shield with Dynamic Fault Detection
- Six External Tamper Sensors with Independent Random Dynamic Patterns
- Temperature and Voltage Tamper Monitor
- Real-Time External Memory Encryption and Integrity Check
- 104-Bit Unique Serial Number (USN)
- Optimal Peripheral Mix Provides Platform Scalability
- External Memory Controller (LPDDR400, SDRAM, SRAM, NOR Flash, NAND Flash)
- NAND Flash Controller with Hardware ECC
- USB 2.0 Host/Device with Internal Transceivers
- Three UART Ports/One I2C Port
- Three SPI Ports with I2S Functionality
- Two ISO 7816 Smart Card Interfaces
- SD/SDHC/SDIO Interface
- 10/100Mbps Ethernet MAC Controller
- Three Timers with PWM Capability
- Up to 126 General-Purpose I/O Pins
- 2-Channel, 10-Bit ADC
- LCD Controller Supporting STN and TFT Displays
- Monochrome LCD Controller
- 16-Channel DMA Controller
- Real-Time Clock
- Advanced Interrupt Controller
Download Data Sheet
MAX32592 Download Data Sheet | Download |
Errata MAX32592 | MAX32592REVB5_NDA.pdf |
Request Full Data Sheet
MAXQ1061 DeepCover Cryptographic Controller for Embedded Devices
- Advanced Cryptographic Tool Box Seamlessly Supports Highly Secure Key Storage
- Certificates Chain Management
- Secure 32KB or 8KB File System Based on Nonvolatile EEPROM (500K Cycles) for Extensive Key and Certificate Storage for MAXQ1061 and MAXQ1062, Respectively
- Symmetric-key: AES-128/-256 (ECB, CBC, CCM)
- Asymmetric-key: ECC NIST P-256, -521, -384 and Brainpool BP-256, -384, -512
- Secure Hash: SHA-256, -384, -512
- MAC Digest: CBC-MAC, HMAC-SHA256, HMAC-SHA384, HMAC-SHA512, ECIES
- Signature Schemes: ECDSA (FIPS 186-4)
- Key Exchange: EC Diffie-Hellman (TLS)
- 128-Bit AES Stream Encryption Engine Over SPI (up to 20Mb/s) Supporting AES-GCM and AES-ECB Modes
- On-Chip Key Generation: ECC, AES
- Random Number Generation: True RNG
- No Firmware Development Required Significantly Reduces Time to Market
- High-Level Functions Simplify SSL/TLS/DTLS Implementations
- TLS/DTLS Key Negotiation (PSK, ECDH, ECDHE)
- ECDSA Based TLS/DTLS Authentication, Digital Signature Generation and Verification
- SSL/TLS/DTLS Packet Encryption (AES)
- MAC Algorithm (HMAC-SHA256)
- Extensive Host/System Services Increase Flexibility and Reduce System Cost
- Watchdog Timer
- Power-On Reset/Brownout Reset
- Secure Boot Function
- Tamper Detection
- Life Cycle Management and Key Loading Protocol
- Flexible File System With User-Programmable Access Conditions for Each Object Software Reset
- Software Reset, Shutdown, and Wake-Up Functions
- Multiple Communication Interface Options for Simpler Connection to a Host Processor
- I²C Slave Controller
- SPI Slave Controller with a Dedicated DMA Channel and 128-Bit AES Stream Encryption Engine Supporting AES-GCM and AES-ECB Modes
Download Data Sheet
MAXQ1061-MAXQ1062 Download Data Sheet | Download |
Errata MAXQ1061 | MAXQ1061REVC2_errata_(abridged.pdf |
Errata MAXQ1061 | MAXQ1061REVC3_NDA.pdf |
Request Full Data Sheet
MAXQ1062 DeepCover Cryptographic Controller for Embedded Devices
- Advanced Cryptographic Tool Box Seamlessly Supports Highly Secure Key Storage
- Certificates Chain Management
- Secure 32KB or 8KB File System Based on Nonvolatile EEPROM (500K Cycles) for Extensive Key and Certificate Storage for MAXQ1061 and MAXQ1062, Respectively
- Symmetric-key: AES-128/-256 (ECB, CBC, CCM)
- Asymmetric-key: ECC NIST P-256, -521, -384 and Brainpool BP-256, -384, -512
- Secure Hash: SHA-256, -384, -512
- MAC Digest: CBC-MAC, HMAC-SHA256, HMAC-SHA384, HMAC-SHA512, ECIES
- Signature Schemes: ECDSA (FIPS 186-4)
- Key Exchange: EC Diffie-Hellman (TLS)
- 128-Bit AES Stream Encryption Engine Over SPI (up to 20Mb/s) Supporting AES-GCM and AES-ECB Modes
- On-Chip Key Generation: ECC, AES
- Random Number Generation: True RNG
- No Firmware Development Required Significantly Reduces Time to Market
- High-Level Functions Simplify SSL/TLS/DTLS Implementations
- TLS/DTLS Key Negotiation (PSK, ECDH, ECDHE)
- ECDSA Based TLS/DTLS Authentication, Digital Signature Generation and Verification
- SSL/TLS/DTLS Packet Encryption (AES)
- MAC Algorithm (HMAC-SHA256)
- Extensive Host/System Services Increase Flexibility and Reduce System Cost
- Watchdog Timer
- Power-On Reset/Brownout Reset
- Secure Boot Function
- Tamper Detection
- Life Cycle Management and Key Loading Protocol
- Flexible File System With User-Programmable Access Conditions for Each Object Software Reset
- Software Reset, Shutdown, and Wake-Up Functions
- Multiple Communication Interface Options for Simpler Connection to a Host Processor
- I²C Slave Controller
- SPI Slave Controller with a Dedicated DMA Channel and 128-Bit AES Stream Encryption Engine Supporting AES-GCM and AES-ECB Modes

DS28C50 DeepCover I2C Secure SHA-3 Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement Only Counter with Authenticated Read
- One GPIO Pin with Optional Authentication Control
- 2Kb of EEPROM for User Data, Key, and Control Registers
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
- I2C Communication, up to 1MHz

DS28C40 Deep Cover Automotive I²C Authenticator
- ECC-P256 Compute Engine
- FIPS 186 ECDSA P256 Signature Generation and Verification
- ECDH Key Exchange for Session Key Establishment
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 198 HMAC for Bidirectional Authentication
- SHA-256 One-Time Pad Encrypted R/W of Configurable Memory Using an ECDH Established Key
- One GPIO Pin with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional ECDSA Certificate Verification to Set On/Off after Multiblock Hash for Secure Boot
- TRNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip Generated Private/Public (Pr/Pu) Key Pairs for ECC Operations
- 6Kb of One-Time Programmable (OTP) for User Data, Keys, and Certificates
- Unique and Unalterable Factory Programmed 64-BitIdentification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- I²C Communication Up to 1MHz
- 3.3V ±10%, -40°C to +125°C Operating Range
- 10-Pin TDFN Package
- 3mm x 4mm TDFN Package
- 3mm x 3mm, Side-Wettable TDFN Package
- AEC-Q100 Grade 1
MAX36210 Security Supervisor with SP800-90A/B TRNG, Tamper Detection, and Cryptography
- Low-Power Security Supervisor Enables Cost Effective Security Solution
- 1KB Battery-Backed NV SRAM with High-Speed Erase on its AES-256 Encryption Key
- 4KB Flash Data Storage
- Battery-Backed Tamper Circuit and RTC
- Low-Current Battery-Backup Operation
- Operates from Single 3.3V Supply
- Security Features Facilitate System-Level Protection
- Tamper Detection with Fast Wipe Key/Data Destruction
- Hardware Accelerators for AES (128/192/256), 3DES, RSA (1024/2048/4096), ECDSA (p256/p384/p521), SHA (1/224/256/384/512)
- True Hardware Random-Number Generator (NIST SP800-90B output and SP800-90A post process)
- Temperature, Voltage and Die Shield Sensors to Detect Attacks
- 2 Pairs of External Sensor Tamper Detects
- Time Stamp for Tamper Event
- Encrypted NV SRAM Data Transfer
- Authentication with Connected Host
- 104-Bit Unique Serial Number
- Integrated Peripherals Allows for Easy Integration into Applications
- Programmable Alarm with External Output
- CPU Supervisor
- SPI, I²C, UART Interfaces
- 4 GPIO Pins
DS28E40 Deep Cover Automotive 1-Wire Authenticator
- ECC-P256 Compute Engine
- FIPS 186 ECDSA P256 Signature and Verification
- ECDH Key Exchange for Session Key Establishment
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 198 HMAC for Bidirectional Authentication
- SHA-256 One-Time Pad Encrypted R/W of Configurable Memory Through ECDH Established Key
- One GPIO Pin with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional ECDSA Certificate Verification to Set On/Off after Multiblock Hash for Secure Boot
- TRNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip-Generated Pr/Pu Key Pairs for ECC Operations
- 6Kb of One-Time Programmable (OTP) for User Data, Keys, and Certificates
- Unique and Unalterable Factory-Programmed 64-Bit Identification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- Single-Contact, 1-Wire Interface Communication with Host at 9.09kbps and 62.5kbps
- 3.3V ±10%, -40°C to +125°C Operating Range
- ±8kV HBM ESD protection of 1-Wire IO Pin
- 10-Pin, 3mm x 4mm TDFN Package
- AEC-Q100 Grade 1
DS2488 1-Wire Dual-Port Link
- Two-Contact Solution Enables Advance TWS Features
- Small Message Exchange between a Case and Earbuds
- High-Speed 512kbps Pass-Through Mode to Transfer Files
- Earbud Battery Charger Power Delivery
- Three GPIO Pins for Optional Feature Control or State Detection
- Full Range of Capabilities for Earbud and Charging Case Detection
- Earbud 64-Bit Identification Number (ROM ID) Readable upon Insertion
- Operating Power Parasitically Derived from the 1-Wire IOA Line
- Detect when in or out of a Charging Case
- Detect a Dead Charging Case Battery
- Minimalist Dual 1-Wire Interface Reduces Cost and Complexity
- Single Dedicated Contact for Communication and Power
- Arbitrated Communication between Two Host Controllers at 90kbps
- Reads and Writes over a Wide 1.71V to 3.63V Voltage Range
- Ideal for Battery Power Consumer Applications
- Small, 1.6mm x 0.9mm x 0.33mm WLP with 0.4mm Ball Pitch
- 1.71V to 3.63V Operating Voltage Range
- High ESD Immunity of IOA Pin: ±8kV HBM (typ)
- -40°C to +85°C Operation

DS28S60 DeepCover Cryptographic Coprocessor with ChipDNA
- Secure Coprocessor with NIST-Compliant Hardware-Based Crypto
- FIPS-180 SHA-256 MAC and FIPS-198 HMAC Hash
- FIPS-197 AES-128 with GCM
- FIPS-186 ECDSA-P256 Elliptic Curve Digital Signature/Verification
- SP800-56A ECDHE-P256 Key Exchange
- SP800-90B Compliant TRNG
- Robust Countermeasures Protect Against Security Attacks
- ChipDNA Produced Key Cryptographically Protects All Stored Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- Enables Fast Time-to-Market with Easy End Application Integration
- Fixed-Function Command Set, No Device-Level Firmware
- C-Source Demos for Examples of SW Development
- 3.6KB Flash Array for Secure Key, Certificate, and Data Storage
- High-Speed Interface for Host Microcontroller Communication
- 20MHz SPI with Mode 0 or Mode 3 Operation
- Supplemental Features Enable Easy Integration into End Applications
- Unique and Unalterable Factory-Programmed, 64-Bit Identification Number (ROM ID)
- Low-Power Operation
- 100nA Power-Down Mode
- 0.35mA Idle
- 12-Pin 3mm x 3mm TDFN

DS28E18 1-Wire® to I2C/SPI Bridge with Command Sequencer
- Operate Remote I2C or SPI Devices Using Single-Contact 1-Wire Interface
- Extending I2C/SPI Communication Distance
- Reduce Six Wires (for SPI) or Four Wires (for I2C) to Two Wires
- 512-Byte Sequencer for Autonomous Operation of Attached Devices
- Two Configurable GPIO Pins for Additional Peripheral Control
- No External Power Required
- DS28E18 Parasitically Powered from 1-Wire
- I2C/SPI Peripheral Power Derived from the 1-Wire Line
- Flexible 1-Wire and I2C/SPI Master Operational Modes
- Supports Standard (11kbps) and Overdrive (90kbps) 1-Wire Communication
- 100kHz, 400kHz, and 1MHz for I2C Slaves
- Up to 2.3MHz for SPI Slaves
- Easy to Integrate
- Small, 2mm x 3mm x 0.75mm, 8-Pin TDFN Package
- -40°C to +85°C Operation
- 2.97V to 3.63V Operating Voltage Range

DS28E38 DeepCover® Secure ECDSA Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Public-Key Authentication Solution to Authenticate Peripherals
- FIPS 186-Compliant ECDSA P256 Signature for Challenge/Response Authentication
- Options for ECDSA Public/Private Key Pair Source Include ChipDNA Generated, Chip Computed, and User Installed
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 2Kbits of EEPROM for User Data, Key, Control Registers, and Certificate
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Single-Contact, 1-Wire Interface Communication with Host at 11.7kbps and 62.5kbps
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
- 2-Pad SFN Package (3.5mm x 6.5mm)

DS28C16 I²C Low-Voltage SHA-3 Authenticator
- Robust Countermeasures Protect Against Security Attacks
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- Secure Storage for Secrets
- 256 Bits of Secure EEPROM for User Data
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- I²C Communications Up to 1MHz
- Operating Range: 1.62V–3.63V, -40°C to +85°C
- 8-Pin, 2mm x 2mm TDFN-EP Package

DS2477 DeepCover Secure SHA-3 Coprocessor with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates and Manages Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Bidirectional Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 2Kb of EEPROM for User Data, Key, and Control Registers
- One Open-Drain GPIO Pin
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Large 1-Wire Block Buffer (126 bytes) for Efficient Data Transfer
- 1-Wire Standard and Overdrive Timing Communication Speeds
- I²C Communication, Up to 1MHz
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)

DS28E36 DeepCover Secure Authenticator
- ECC-256 Compute Engine
- FIPS 186 ECDSA P256 Signature and Verification
- ECDH Key Exchange with Authentication Prevents Man-in-the-Middle Attacks
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 180 MAC for Secure Download/Boot Operations
- FIPS 198 HMAC for Bidirectional Authentication and Optional GPIO Control
- Two GPIO Pins with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional Set On/Off after Multiblock Hash for Secure Boot/Download
- RNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip Generated Pr/Pu Key Pairs for ECC Operations
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 8Kbits of EEPROM for User Data, Keys, and Certificates
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- Single-Contact 1-Wire Interface Communication with Host at 11.7kbps and 62.5kbps
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
MAX66240 DeepCover Secure Authenticator with ISO 15693, SHA-256, and 4Kb User EEPROM
- Dedicated Hardware-Accelerated SHA Engine
- Strong Authentication with a High Bit Count User-Programmable Secret and Input Challenge
- 4096 Bits of User EEPROM with User-Programmable R/W Protection Options Including OTP/EPROM Emulation Mode
- Unique Factory-Programmed 64-Bit Identification Number
- ISO/IEC 15693: Up to 26kbps
- ±2kV HBM ESD Protection for All Pins
DS28C39 DeepCover Secure ECDSA Bidirectional Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- ECDSA Authenticated R/W of Stored Data and Counter
- Efficient Public-Key Authentication Solution to Authenticate Peripherals
- FIPS 186-Compliant ECDSA P256 Signature for Challenge/Response Authentication
- ChipDNA Generated Public/Private Key Pair.
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- 2Kb of EEPROM for User Data, Key, Control Registers, and Certificate
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- I2C Communication: Up to 200kHz
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)

DS28E16 1-Wire Secure SHA-3 Authenticator
- Robust Countermeasures Protect Against Security Attacks
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement-Only Counter with Authenticated Read
- Secure Storage for Secrets
- 256 Bits of Secure EEPROM for User Data
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Advanced 1-Wire Protocol Minimizes Interface to Single Contact
- Full-Time Overdrive Communication Speed
- Internal Parasite Power Capacitor
- Operating Range: 1.71V–3.63V, -40°C to +85°C
- WLP, TDFN-EP, and SFN Packages
- ±8kV HBM ESD Protection (typ)
- 3.5µA (typ) Input Load Current
MAX32561 DeepCover Secure Arm Cortex-M3 Flash Microcontroller
- Arm Cortex M3 Processor Core Allows for Easy Integration into Applications
- 108MHz Core Operating Frequency Through PLL
- 1MB Dual-Bank Flash Memory with Cache
- 384KB System SRAM
- 8KB AES Self-Encrypted NVSRAM
- Security Features Facilitate System-Level Protection
- ISO 14443 type A/B EMV Compliant Contactless Reader with Internal Transceiver
- Secure Boot Loader with Public Key Authentication
- AES, DES and SHA Hardware Accelerators
- Modulo Arithmetic Hardware Accelerator (MAA) Supporting RSA, DSA, and ECDSA
- 9-Line Secure Keypad Controller
- Hardware True Random-Number Generator
- Die Shield with Dynamic Fault Detection
- 6 External Tamper Sensors with Independent Random Dynamic Patterns
- 256-Bit Flip-Flop-Based Battery-Backup AES Key Storage
- Temperature and Voltage Tamper Monitor
- Real-Time Clock
- Integrated Peripherals Reduce External Component Count
- Triple-Track Magnetic Stripe Head Interface
- One ISO 7816 Smart Card Interface with Integrated Transceiver (1.8V, 3V, and 5V) and One Smart Card Interface Only
- USB 2.0 Device with Internal Transceiver and Dedicated PLL
- 2 SPI Ports, 2 UART Ports, and I²C Controller
- 6 Timers, 2 with PWM Capability
- Up to 39 General-Purpose I/O Pins
- 1-Channel, 10-Bit ADC
- 4-Channel DMA Controller
- 1 SPI Execute in Place (XiP) Master
- Power Management Optimizes Battery Life and Reduces Active Power Consumption
- Single 3.3V Supply Operation*
- Integrated Battery-Backup Switch
- Clock Gating Function
- Low-Current Battery-Backup Operation
Download Data Sheet
Errata MAX32561 | MAX32561_A7_NDA_Rev1.pdf |
NDA Required. Request Full Data Sheet and Software
MAX32592 DeepCover Secure Microcontroller with ARM926EJ-S Processor Core
- High Performance CPU platform Enables Feature Rich OS
- Arm926EJ-S™ Processor Core with 16KB Data Cache and 32KB Instruction Cache
- 4KB Instruction TCM, 4KB Data TCM
- Up to 400MHz Core Operating Frequency
- Up to 200MHz Multilayer AHB Bus Matrix
- Up to 100MHz APB Bus Matrix
- 384KB System SRAM
- Flexible Clock Prescalers
- Configurable Low-Power Modes
- Security Features Facilitates System-Level Protection
- Secure Bootloader with Public Key Authentication
- 256-Bit Flip-Flop-Based Nonvolatile AES Key Storage
- 24KB AES User-Encryptable NV SRAM
- 2KB User-Programmable OTP
- AES, DES, and SHA Hardware Accelerators
- Modulo Arithmetic Hardware Accelerator (MAA) Supporting RSA, DSA, and ECDSA
- Secure Keypad Controller
- Hardware True Random Number Generator
- Die Shield with Dynamic Fault Detection
- Six External Tamper Sensors with Independent Random Dynamic Patterns
- Temperature and Voltage Tamper Monitor
- Real-Time External Memory Encryption and Integrity Check
- 104-Bit Unique Serial Number (USN)
- Optimal Peripheral Mix Provides Platform Scalability
- External Memory Controller (LPDDR400, SDRAM, SRAM, NOR Flash, NAND Flash)
- NAND Flash Controller with Hardware ECC
- USB 2.0 Host/Device with Internal Transceivers
- Three UART Ports/One I2C Port
- Three SPI Ports with I2S Functionality
- Two ISO 7816 Smart Card Interfaces
- SD/SDHC/SDIO Interface
- 10/100Mbps Ethernet MAC Controller
- Three Timers with PWM Capability
- Up to 126 General-Purpose I/O Pins
- 2-Channel, 10-Bit ADC
- LCD Controller Supporting STN and TFT Displays
- Monochrome LCD Controller
- 16-Channel DMA Controller
- Real-Time Clock
- Advanced Interrupt Controller
Download Data Sheet
MAX32592 Download Data Sheet | Download |
Errata MAX32592 | MAX32592REVB5_NDA.pdf |
Request Full Data Sheet
MAXQ1061 DeepCover Cryptographic Controller for Embedded Devices
- Advanced Cryptographic Tool Box Seamlessly Supports Highly Secure Key Storage
- Certificates Chain Management
- Secure 32KB or 8KB File System Based on Nonvolatile EEPROM (500K Cycles) for Extensive Key and Certificate Storage for MAXQ1061 and MAXQ1062, Respectively
- Symmetric-key: AES-128/-256 (ECB, CBC, CCM)
- Asymmetric-key: ECC NIST P-256, -521, -384 and Brainpool BP-256, -384, -512
- Secure Hash: SHA-256, -384, -512
- MAC Digest: CBC-MAC, HMAC-SHA256, HMAC-SHA384, HMAC-SHA512, ECIES
- Signature Schemes: ECDSA (FIPS 186-4)
- Key Exchange: EC Diffie-Hellman (TLS)
- 128-Bit AES Stream Encryption Engine Over SPI (up to 20Mb/s) Supporting AES-GCM and AES-ECB Modes
- On-Chip Key Generation: ECC, AES
- Random Number Generation: True RNG
- No Firmware Development Required Significantly Reduces Time to Market
- High-Level Functions Simplify SSL/TLS/DTLS Implementations
- TLS/DTLS Key Negotiation (PSK, ECDH, ECDHE)
- ECDSA Based TLS/DTLS Authentication, Digital Signature Generation and Verification
- SSL/TLS/DTLS Packet Encryption (AES)
- MAC Algorithm (HMAC-SHA256)
- Extensive Host/System Services Increase Flexibility and Reduce System Cost
- Watchdog Timer
- Power-On Reset/Brownout Reset
- Secure Boot Function
- Tamper Detection
- Life Cycle Management and Key Loading Protocol
- Flexible File System With User-Programmable Access Conditions for Each Object Software Reset
- Software Reset, Shutdown, and Wake-Up Functions
- Multiple Communication Interface Options for Simpler Connection to a Host Processor
- I²C Slave Controller
- SPI Slave Controller with a Dedicated DMA Channel and 128-Bit AES Stream Encryption Engine Supporting AES-GCM and AES-ECB Modes
Download Data Sheet
MAXQ1061-MAXQ1062 Download Data Sheet | Download |
Errata MAXQ1061 | MAXQ1061REVC2_errata_(abridged.pdf |
Errata MAXQ1061 | MAXQ1061REVC3_NDA.pdf |
Request Full Data Sheet
MAXQ1062 DeepCover Cryptographic Controller for Embedded Devices
- Advanced Cryptographic Tool Box Seamlessly Supports Highly Secure Key Storage
- Certificates Chain Management
- Secure 32KB or 8KB File System Based on Nonvolatile EEPROM (500K Cycles) for Extensive Key and Certificate Storage for MAXQ1061 and MAXQ1062, Respectively
- Symmetric-key: AES-128/-256 (ECB, CBC, CCM)
- Asymmetric-key: ECC NIST P-256, -521, -384 and Brainpool BP-256, -384, -512
- Secure Hash: SHA-256, -384, -512
- MAC Digest: CBC-MAC, HMAC-SHA256, HMAC-SHA384, HMAC-SHA512, ECIES
- Signature Schemes: ECDSA (FIPS 186-4)
- Key Exchange: EC Diffie-Hellman (TLS)
- 128-Bit AES Stream Encryption Engine Over SPI (up to 20Mb/s) Supporting AES-GCM and AES-ECB Modes
- On-Chip Key Generation: ECC, AES
- Random Number Generation: True RNG
- No Firmware Development Required Significantly Reduces Time to Market
- High-Level Functions Simplify SSL/TLS/DTLS Implementations
- TLS/DTLS Key Negotiation (PSK, ECDH, ECDHE)
- ECDSA Based TLS/DTLS Authentication, Digital Signature Generation and Verification
- SSL/TLS/DTLS Packet Encryption (AES)
- MAC Algorithm (HMAC-SHA256)
- Extensive Host/System Services Increase Flexibility and Reduce System Cost
- Watchdog Timer
- Power-On Reset/Brownout Reset
- Secure Boot Function
- Tamper Detection
- Life Cycle Management and Key Loading Protocol
- Flexible File System With User-Programmable Access Conditions for Each Object Software Reset
- Software Reset, Shutdown, and Wake-Up Functions
- Multiple Communication Interface Options for Simpler Connection to a Host Processor
- I²C Slave Controller
- SPI Slave Controller with a Dedicated DMA Channel and 128-Bit AES Stream Encryption Engine Supporting AES-GCM and AES-ECB Modes

DS28C50 DeepCover I2C Secure SHA-3 Authenticator with ChipDNA PUF Protection
- Robust Countermeasures Protect Against Security Attacks
- Patented Physically Unclonable Function Secures Device Data
- Actively Monitored Die Shield Detects and Reacts to Intrusion Attempts
- All Stored Data Cryptographically Protected from Discovery
- Efficient Secure Hash Algorithm Authenticates Peripherals
- FIPS 202-Compliant SHA-3 Algorithm for Challenge/Response Authentication
- FIPS 198-Compliant Keyed-Hash Message Authentication Code (HMAC)
- TRNG with NIST SP 800-90B Compliant Entropy Source
- Supplemental Features Enable Easy Integration into End Applications
- 17-Bit One-Time Settable, Nonvolatile Decrement Only Counter with Authenticated Read
- One GPIO Pin with Optional Authentication Control
- 2Kb of EEPROM for User Data, Key, and Control Registers
- Unique and Unalterable Factory Programmed 64-Bit Identification Number (ROM ID)
- Operating Range: 3.3V ±10%, -40°C to +85°C
- 6-Pin TDFN-EP Package (3mm x 3mm)
- I2C Communication, up to 1MHz

DS28C40 Deep Cover Automotive I²C Authenticator
- ECC-P256 Compute Engine
- FIPS 186 ECDSA P256 Signature Generation and Verification
- ECDH Key Exchange for Session Key Establishment
- ECDSA Authenticated R/W of Configurable Memory
- SHA-256 Compute Engine
- FIPS 198 HMAC for Bidirectional Authentication
- SHA-256 One-Time Pad Encrypted R/W of Configurable Memory Using an ECDH Established Key
- One GPIO Pin with Optional Authentication Control
- Open-Drain, 4mA/0.4V
- Optional SHA-256 or ECDSA Authenticated On/Off and State Read
- Optional ECDSA Certificate Verification to Set On/Off after Multiblock Hash for Secure Boot
- TRNG with NIST SP 800-90B Compliant Entropy Source with Function to Read Out
- Optional Chip Generated Private/Public (Pr/Pu) Key Pairs for ECC Operations
- 6Kb of One-Time Programmable (OTP) for User Data, Keys, and Certificates
- Unique and Unalterable Factory Programmed 64-BitIdentification Number (ROM ID)
- Optional Input Data Component to Crypto and Key Operations
- I²C Communication Up to 1MHz
- 3.3V ±10%, -40°C to +125°C Operating Range
- 10-Pin TDFN Package
- 3mm x 4mm TDFN Package
- 3mm x 3mm, Side-Wettable TDFN Package
- AEC-Q100 Grade 1