MAX32552

DeepCover Secure Cortex-M3 Flash Microcontroller

Secure Cortex-M3 Flash Microcontroller with XiP QuadSPI interface


Description

DeepCover®embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible.

The DeepCover Secure microcontroller (MAX32552) provides an interoperable, secure, and cost-effective solution to build new generations of trusted devices such as mobile chip and pin pads. The MAX32552 is based on a Cortex®-M3 processor with 1MB of embedded flash, 384KB of system RAM, 8KB of battery-backed AES self-encrypted NVSRAM. In addition to a high-performance QSPI® interface for secure code execution and data storage, it includes most of the essential functions of mobile POS terminal including a cryptographic engine, a true random number generator, battery-backed RTC, environmental and tamper detection circuitry, a magnetic stripe reader, a smart card controller with embedded transceiver to directly support 1.8V, 3.3V, and 5V cards, and an integrated secure keypad controller. It also provides a seamless interface to monochrome graphic displays and includes a vast array of peripherals, SPIs, UARTs, DMA, ADC, and DAC that add flexibility to control and differentiate the system design.

Key Features

  • ARM® Cortex M3 Processor Core Allows for Easy Integration into Applications
    • 108MHz Core Operating Frequency Through PLL
    • 1MB Dual-Bank Flash Memory with Cache
    • 384KB System SRAM
    • 8KB AES Self-Encrypted NVSRAM
  • Security Features Facilitate System-Level Protection
    • Secure Boot Loader with Public Key Authentication
    • AES, DES and SHA Hardware Accelerators
    • Modulo Arithmetic Hardware Accelerator (MAA) Supporting RSA, DSA, and ECDSA
    • 8-Line Secure Keypad Controller
    • Hardware True Random-Number Generator
    • Die Shield with Dynamic Fault Detection
    • 6 External Tamper Sensors with Independent Random Dynamic Patterns
    • 256-Bit Flip-Flop-Based Battery-Backup AES Key Storage
    • Temperature and Voltage Tamper Monitor
    • Real-Time Clock
  • Integrated Peripherals Reduce External Component Count
    • Triple-Track Magnetic Stripe Head Interface
    • Two ISO 7816 Smart Card UART with one that integates a ISO7816 transceiver (1.8V, 3V, and 5V)
    • USB 2.0 Device with Internal Transceiver and Dedicated PLL
    • 3 SPI Ports, 2 UART Ports, and 2 I²C Controller
    • 6 Timers, 4 with PWM Capability
    • Up to 64 General-Purpose I/O Pins
    • 2-Channel, 10-Bit ADC and 1-Channel, 8-Bit DAC
    • Monochrome LCD Controller
    • 4-Channel DMA Controller
    • 1 SPI Execute in Place (XiP) Master
  • Power Management Optimizes Battery Life and
    • Reduces Active Power Consumption
    • Single 3.3V Supply Operation*
    • Integrated Battery-Backup Switch
    • Clock Gating Function,
    • Low-Current Battery-Backup Operation

Applications/Uses

  • ATM Keyboards
  • Contact Pin Pads
  • EMV Card Reader
  • PCI Mobile Payment Terminals (mPOS)
Part Number MCU Core Core Clock Speed
(MHz)
Data Processing Internal Flash
(KBytes)
Internal SRAM
(KBytes)
USARTs SPI Bus I2C Bus USB GPIO Pins PWM Timer Features Package/Pins
max max
MAX32552 NEW! ARM Cortex-M3 108 32-bit 1000 384 2 3 2 Master
1 x 2.0 FS Device
Device Including Transceiver
64 4
Capture/Compare
Watchdog
CTBGA-CU/121
See All Microcontrollers (48)
Pricing Notes:
This pricing is BUDGETARY, for comparing similar parts. Prices are in U.S. dollars and subject to change. Quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. For volume-specific and version-specific prices and delivery, please see the price and availability page or contact an authorized distributor.

Quality and Environmental Data

Request Reliability Report for: MAX32552 
Lead-Free Package Tin (Sn) Whisker Reports

Related Resources


MAXREFDES155
MAXREFDES155#: DeepCover Embedded Security in an IoT: Public-Key Secured Data Paths


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DeepCover Secure Cortex-M3 Flash Microcontroller

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  • Security Features Facilitate System-Level Protection
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