Maxim's approach to RF power amplifier linearization, called RF predistortion, repartitions portions of the predistortion algorithm from the digital domain to the analog/RF domain. This implementation is sometimes called analog predistortion. The text below will identify the key architectural blocks which comprise Maxim's RF Power Linearizer (RFPAL) and describe their function.
Nearly the entire Correction Processor block shown in Figure 7 is implemented using RF/analog circuits resulting in very low power consumption, wide bandwidth performance and compact circuits compared to the equivalent digital implementation.
Figure 7. RFPAL architecture and functional block diagram
Correction Processor block, the RFIN signal passes through a quadrature phase shifter (QPS) to create an I and Q signal [RFIN(I), RFIN(Q)], which is used in multiple locations. The envelope power of RFIN(I) and RFIN(Q) is also used in the Volterra Series Generator block to create the even order IM terms by applying a non-linear transformation. In order to compensate for PA memory effects, four different sets of coefficients are created based on delay terms (τ1 to τ4) ranging from 0ns to 300ns (Figure 8a). All coefficients are individually controlled and generated by the digital controller running a proprietary adaptation algorithm. For each of the memory terms, the even order correction functions are summed and then multiplied with their corresponding RFIN(I) and RFIN(Q) signals generated by the QPS. This final multiply converts the even order terms into odd orders terms. The I and Q correction signals are then summed creating the RFOUT correction signal. The Correction Processor uses a full 360° modulator enabling it to correct IM terms of any phase and magnitude. The digital controller adapts the coefficients based on the information derived from the RFFB feedback signal and applies them to the Correction Processor until an optimal set of coefficients is found that minimizes the cost function (error metric).
Figure 8a. Volterra series generator block diagram
Figure 8b. Volterra series equation
The Monitor block is implemented largely in the digital domain, as functions like FFTs and error metric generation are better suited to an implementation that uses digital signal processing (DSP). As seen in Figure 7, the Monitor inputs include the down-converters and ADCs required to provide the spectrally resolved data used by the DSP. The integration of the RFFB ADC is a significant difference compared to DPD which relies on external down-converters and ADCs. Maxim's unique partitioning approach results in a monolithic and highly integrated solution that maintains the flexibility of digital approaches while offering the simplicity and low power consumption of analog approaches.