Product Details
The device accepts FEC-encoded CMOS data (symbols) on up to four 10-bit input ports that accept up to 32 time-interleaved digital data streams each. Each channel features an individually configurable QAM mapper, RRC filter, and arbitrary rate resampler (ARR). The device performs pulse shaping, resampling, interpolation and quadrature modulation of input data, supporting all data rates defined in DOCSIS and DVB-C. A cascade of interpolation filters, complex modulators, and channel combiners allow modulation of the signal to any frequency from 45MHz to 1003MHz. Integrated direct digital frequency synthesizers allow positioning of the QAM channels with a resolution of 125Hz. The interpolation filters and resamplers provide linear phase and excellent gain flatness. Output data from the last modulator is fed to a digital-predistortion (DPD) block that can be used to correct distortion in the RF-DAC and output amplifiers. The output interface to the RF-DAC consists of four 14-bit interleaved LVDS buses that operate up to 1250Mwps each.
Key Features
- High-Density: Scalable Up to 128 QAM Channels
- Factory Preset for 8, 16, 24, 32, 48, 64, 96, or 128 QAM Channels
- Soft-Key Field-Upgradeable in Steps of 8 QAMs
- RRC Filters Support ITU-T J.83 Annex A, B, and C
- 1MHz to 8MHz Channel Bandwidth
- Full Carrier Agility within Each of Four 192MHz Blocks
- Block Agility within 950MHz Output Bandwidth
- Reconfigurable Without Service Interruption
- DOCSIS 3.0 DRFI Compliant
- Input Symbol Rate: 1Msym/s to 7.14Msym/s
- Independently Set for Each Channel
- Integrated QAM Mapper (16/32/64/128/256-QAM)
- Supports All ITU-T J.83-Defined Constellations
- Four CMOS Input Ports Support Up to 1024-QAM
- Programmable Digital Predistortion
- Four 14-Bit LVDS Output Ports Operate Up to 1250Mwps Each
- Drives MAX5882 and MAX5879A RF-DACs
- Low-Power Operation
- 3.3W at 128 (6MHz) QAMs, fS = 4608Msps
Applications/Uses
- Edge QAM, CMTS, and CCAP
- QAM Modulators for Video Distribution
Technical Docs
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Description
Features
- Evaluates the MAX5880 Up to 128 QAM Channels
- Single 5.5V Input-Voltage Supply
- Maximum 5Gsps Update Rate
- Direct Interface with Maxim HSDCEP Data Source Board Using QSH Connectors (Order HSDCEP)
- Direct Interface with MAX5882 or MAX5879A EV Kits
- Windows XP-, Windows Vista-, and Windows 7-Compatible Software for SPI/I²C Interfaces
- On-Board SPI Interface Control for MAX5880
- On-Board I²C Interface Control for MAX6642 Temperature Sensor
- GUI Controls for HSDCEP Operation
- Pseudorandom Bit Sequence (PRBS) Test Pattern Files
- Proven 14-Layer PCB Design
- Fully Assembled and Tested
Support & Training
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Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal
Parameters
Key Features
- High-Density: Scalable Up to 128 QAM Channels
- Factory Preset for 8, 16, 24, 32, 48, 64, 96, or 128 QAM Channels
- Soft-Key Field-Upgradeable in Steps of 8 QAMs
- RRC Filters Support ITU-T J.83 Annex A, B, and C
- 1MHz to 8MHz Channel Bandwidth
- Full Carrier Agility within Each of Four 192MHz Blocks
- Block Agility within 950MHz Output Bandwidth
- Reconfigurable Without Service Interruption
- DOCSIS 3.0 DRFI Compliant
- Input Symbol Rate: 1Msym/s to 7.14Msym/s
- Independently Set for Each Channel
- Integrated QAM Mapper (16/32/64/128/256-QAM)
- Supports All ITU-T J.83-Defined Constellations
- Four CMOS Input Ports Support Up to 1024-QAM
- Programmable Digital Predistortion
- Four 14-Bit LVDS Output Ports Operate Up to 1250Mwps Each
- Drives MAX5882 and MAX5879A RF-DACs
- Low-Power Operation
- 3.3W at 128 (6MHz) QAMs, fS = 4608Msps
Applications/Uses
- Edge QAM, CMTS, and CCAP
- QAM Modulators for Video Distribution
Description
The device accepts FEC-encoded CMOS data (symbols) on up to four 10-bit input ports that accept up to 32 time-interleaved digital data streams each. Each channel features an individually configurable QAM mapper, RRC filter, and arbitrary rate resampler (ARR). The device performs pulse shaping, resampling, interpolation and quadrature modulation of input data, supporting all data rates defined in DOCSIS and DVB-C. A cascade of interpolation filters, complex modulators, and channel combiners allow modulation of the signal to any frequency from 45MHz to 1003MHz. Integrated direct digital frequency synthesizers allow positioning of the QAM channels with a resolution of 125Hz. The interpolation filters and resamplers provide linear phase and excellent gain flatness. Output data from the last modulator is fed to a digital-predistortion (DPD) block that can be used to correct distortion in the RF-DAC and output amplifiers. The output interface to the RF-DAC consists of four 14-bit interleaved LVDS buses that operate up to 1250Mwps each.
Technical Docs
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal