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Quad-Band TDD-WCDMA RF-to-Bits Radio Receiver

Industry's Only Complete RF-to-Digital Bits Receive Subsystem for 3GPP WCDMA/TDD Applications

Product Details

The MAX2548 quad-band direct-conversion RF-to-bits radio receiver is designed for 1x (3.84Mcps) and 2x (7.68Mcps) TDD-WCDMA applications. The part supports operation in the 915MHz to 921MHz, 1900MHz to 1920MHz, 2010MHz to 2025MHz, and 2050MHz to 2082MHz frequency bands.

The unique RF-to-bits architecture of the MAX2548 integrates 4 LNAs, quadrature mixers, baseband anti-aliasing filters, programmable gain baseband amplifiers, high dynamic range I and Q sigma-delta analog-to-digital converters (ADCs), a fractional-N frequency synthesizer for local oscillator (LO) generation, and a fractional-N frequency synthesizer for sampling clock generation. Data is transferred from the radio to the baseband/DSP by a digital 1-bit sigma-delta modulated I and Q bit-stream through an LVDS-like interface. All decimation, compensation, and channel filtering is performed in the digital domain in compliance with the MAX-PHY digital section definition. The operating mode of the radio is fully programmable by a 3-wire serial interface.

The MAX2548 is specified for operation in the extended -40°C to +85°C temperature range and is available in a 7mm x 7mm x 1.4mm fcLGA package with exposed paddle (EP).

Key Features

  • Complete RF In to Digital Bits Out Radio Receiver Subsystem
  • Supports 1x (3.84Mcps) and 2x (7.68Mcps) TDD-WCDMA Operation in the Following Bands:
    • 915MHz to 921MHz
    • 1900MHz to 1920MHz
    • 2010MHz to 2025MHz
    • 2050MHz to 2082MHz
  • MAX-PHY Digital Rx Interface with Single-Bit I and Q Bitstreams
  • Complete Two-Chip TDD-WCDMA Solution with MAX2598 Transmitter
  • High Dynamic Range Sigma-Delta ADCs Allow Simple AGC Implementation with Switched Gain States
  • On-Chip Fractional-N Frequency Synthesizers for LO and Sampling Clock Generation
  • Dual Buffered Reference Outputs to Drive Transmit IC and Baseband/DSP
  • Operation Controlled Entirely by 3-Wire Serial Interface; No Analog Control Signals Necessary

Applications/Uses

  • TDD-WCDMA Handsets and Data Cards
  • TD TV Receivers

Simplified Block Diagram

MAX2548: Typical Operating Circuit MAX2548: Typical Operating Circuit Zoom icon

Technical Docs

Design & Development

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Parameters

Key Features

  • Complete RF In to Digital Bits Out Radio Receiver Subsystem
  • Supports 1x (3.84Mcps) and 2x (7.68Mcps) TDD-WCDMA Operation in the Following Bands:
    • 915MHz to 921MHz
    • 1900MHz to 1920MHz
    • 2010MHz to 2025MHz
    • 2050MHz to 2082MHz
  • MAX-PHY Digital Rx Interface with Single-Bit I and Q Bitstreams
  • Complete Two-Chip TDD-WCDMA Solution with MAX2598 Transmitter
  • High Dynamic Range Sigma-Delta ADCs Allow Simple AGC Implementation with Switched Gain States
  • On-Chip Fractional-N Frequency Synthesizers for LO and Sampling Clock Generation
  • Dual Buffered Reference Outputs to Drive Transmit IC and Baseband/DSP
  • Operation Controlled Entirely by 3-Wire Serial Interface; No Analog Control Signals Necessary

Applications/Uses

  • TDD-WCDMA Handsets and Data Cards
  • TD TV Receivers

Description

The MAX2548 quad-band direct-conversion RF-to-bits radio receiver is designed for 1x (3.84Mcps) and 2x (7.68Mcps) TDD-WCDMA applications. The part supports operation in the 915MHz to 921MHz, 1900MHz to 1920MHz, 2010MHz to 2025MHz, and 2050MHz to 2082MHz frequency bands.

The unique RF-to-bits architecture of the MAX2548 integrates 4 LNAs, quadrature mixers, baseband anti-aliasing filters, programmable gain baseband amplifiers, high dynamic range I and Q sigma-delta analog-to-digital converters (ADCs), a fractional-N frequency synthesizer for local oscillator (LO) generation, and a fractional-N frequency synthesizer for sampling clock generation. Data is transferred from the radio to the baseband/DSP by a digital 1-bit sigma-delta modulated I and Q bit-stream through an LVDS-like interface. All decimation, compensation, and channel filtering is performed in the digital domain in compliance with the MAX-PHY digital section definition. The operating mode of the radio is fully programmable by a 3-wire serial interface.

The MAX2548 is specified for operation in the extended -40°C to +85°C temperature range and is available in a 7mm x 7mm x 1.4mm fcLGA package with exposed paddle (EP).

Simplified Block Diagram

MAX2548: Typical Operating Circuit MAX2548: Typical Operating Circuit Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal