MAX2547

WCDMA/HSPA Band I RF-to-Bits Femto-Basestation Radio Receiver

Industry's First Complete RF-to-Digital Bits Receive Subsystem for WCDMA Band 1 Femto-Basestation Applications


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Description

The MAX2547 direct-conversion RF-to-bits radio receiver is designed for Band I (1920MHz to 1980MHz) WCDMA/HSPA femto-basestation applications. The receiver also features a separate dedicated receive path for the 2110MHz to 2170MHz band that enables monitoring of macro cell downlink activity (sniffer mode).

The unique RF-to-bits architecture of the MAX2547 integrates 2 LNAs, quadrature mixers, baseband anti-aliasing filters, programmable gain baseband amplifiers, high dynamic range I and Q sigma-delta analog-to-digital converters (ADCs), a fractional-N frequency synthesizer for local oscillator (LO) generation, and a fractional-N frequency synthesizer for sampling clock generation. Data is transferred from the radio to the baseband/DSP by a digital 1-bit sigma-delta-modulated I and Q bitstream through an LVDS-like interface. All decimation, compensation, and channel filtering is performed in the digital domain. Digital IP blocks are available from Maxim. The operating mode of the radio is fully programmable by a 3-wire serial interface.

The MAX2547 is specified for operation in the extended -40°C to +85°C temperature range and is available in a 7mm x 7mm x 1.4mm fcLGA package with exposed paddle (EP).

Key Features

  • Complete RF-to-Digital-Bits-Out Radio Receiver Subsystem
  • Supports Band I (1920MHz to 1980MHz) WCDMA/HSPA Operation
  • Supports Sniffer Mode for Monitoring of Macro Cell Activity to Optimize Operating Parameters
  • Supports GSM Sniffer Mode in EGSM and DCS Bands
  • TS25.104 Compliant
  • Low Power Consumption; Typically 190mW at +2.85V
  • MAX-PHY Digital Rx Interface with Single-Bit I and Q Bitstreams Eliminates Analog Baseband Signals
  • Digital Output Bit Rate: 153.6Mbps in WCDMA Mode and 26Mbps in GSM Mode
  • Complete Two-Chip WCDMA/HSPA Basestation Radio Solution with MAX2599 Transmitter Reference Design Available
  • High Dynamic Range Sigma-Delta ADCs Allow Simple AGC Implementation with Switched Gain States
  • On-Chip Fractional-N Frequency Synthesizers for LO and Sampling Clock Generation
  • Dual Buffered Reference Outputs to Drive Transmit IC and Baseband/DSP
  • Operation Controlled Entirely by 3-Wire Serial Interface; No Analog Control Signals Necessary
  • Rail-to-Rail Outputs Controlled by Serial Interface for External Component Control

Applications/Uses

  • WCDMA/HSPA Band I Femto-Basestations
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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