Simplified Block Diagram
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- Fully Monolithic Direct-Conversion Receivers
- Eliminates External IF SAW + IF AGC + I/Q Demod
- Meets all 3GPP Receiver's Standard Requirements with at Least 3dB Margin on Eb/No
- Operates from a +2.7V to +3.3V Single Supply
- Over 90dB of RF+ Baseband Gain-Control Range
- Channel Selectivity Over 40dB
- Receiver Current Consumption ≈ 32mA
- On-Chip DC Offset Cancellation
- Compatible with Various CMOS Logic Levels
- IMT2000 Handsets
- TD-SCDMA Handsets
- UMTS Handsets
- WCDMA Band II (PCS) Handsets
- WCDMA TDD Handsets
The MAX2390 family of receiver ICs have over 90dB of dynamic gain control, and typical noise figure of 2.7dB referred to LNA input. Each receiver consists of an ultra-low-current low-noise amplifier (LNA) with on-chip output matching and a two-step gain control. The zero-IF demodulator has a differential circuit topology for minimum LO leakage to receiver's input. The channel selectivity is done completely in the baseband section of the receiver with an on-chip lowpass filter. The AGC section has over 50dB of gain-control range. LO quadrature generation is done on-chip through a divide-by-2 prescaler. The DC offset cancellation in the I/Q baseband channels is done fully on-chip using a DC servo loop. To quickly correct for large DC offset transients in minimal time, very fast settling time is obtained by optimization of the DC-offset-cancellation circuit's time constant.
The MAX2390 family includes a 3-wire serial bus for configuring the different receiver modes. They also include a SHDN-bar pin for full device shutdown. The receivers are fabricated using an advanced high-frequency SiGe BiCMOS process. The ICs operate from a single +2.7V to +3.3V supply and are housed in a small 28-pin leadless QFN-EP package (5mm x 5mm).