DS33R11

Ethernet Mapper with Integrated T1/E1/J1 Transceiver


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Description

The DS33R11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream.

The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33R11 can operate with an inexpensive external processor.

DS33R11: Functional Diagram DS33R11: Functional Diagram Enlarge+

Key Features

  • 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
  • Integrated T1/E1/J1 Framer and LIU
  • HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
  • Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
  • Programmable BERT for Serial (TDM) Interface
  • External 16MB, 100MHz SDRAM Buffering
  • Parallel Microprocessor Interface
  • 1.8V, 3.3V Supplies
  • Reference Design Routes on Two Signal Layers
  • IEEE 1149.1 JTAG Support

Applications/Uses

  • Ethernet Delivery Over T1/E1/J1
  • LAN Extension
  • Transparent LAN Service

Technical Documents

App Note 4233 Carrier Ethernet Service Demarcation in Optical Networks
App Note 4118 DS33R11 Multichip-Module BSDL Testing
Tutorial 3849 Ethernet-over-PDH Technology Overview

Quality and Environmental Data

Product Reliability Reports: DS33R11.pdf 
Lead-Free Package Tin (Sn) Whisker Reports

CAD Symbols and Footprints

  • DS33R11+
  • Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

    Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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