DS26401

Octal T1/E1/J1 Framer


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Description

The DS26401 is an octal, software-selectable T1, E1, or J1 framer. It is composed of 8 framer/formatters and a system (backplane) interface. Each framer has an HDLC controller that can be mapped to any DS0 or FDL (T1)/Sa (E1) bit. The DS26401 also includes a full-feature BERT device, which can be used with any of the 8 T1/E1 ports, and an internal clock adapter useful for creating synchronous, high-frequency backplane timing. The DS26401 is controlled through an 8-bit parallel port that can be configured for nonmultiplexed Intel or Motorola operation.
DS26401: Block Diagram DS26401: Block Diagram Enlarge+

Key Features

  • 8 Independent, Full-Featured T1/E1/J1 Framers/Formatters
  • Independent Transmit and Receive Paths
  • Flexible Signaling Extraction and Insertion
  • Alarm Detection and Insertion
  • Transmit Synchronizer
  • AMI, B8ZS, HDB3, NRZ Line Coding
  • Performance Monitor Counters
  • BOC Message Controller (T1)
  • Two-Frame Elastic Store Buffers for Each Transmitter and Receiver
  • One HDLC Controller per Framer
  • RAI-CI and AIS-CI Support
  • Full-Feature BERT can be Mapped to Any Port
  • Flexible TDM Backplane Supports Bus Rates from 1.544MHz to 16.384MHz
  • Internal Clock Generator (CLAD) Supplies 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
  • JTAG Test Port
  • Single 3.3V Supply with 5V Tolerant Inputs
  • 17mm x 17mm, 256-Pin BGA (1.00mm Pitch)

Applications/Uses

  • Add/Drop Multiplexers
  • Automatic Teller Machine Systems
  • Central Office Equipment
  • Customer Premise Equipment
  • DSLAM Backplane
  • IMA
  • Line Cards
  • PBXs
  • Routers/Switches
  • Routers/Switches
  • Timing Systems
  • WAN Interface
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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