MAX3890

+3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and LVDS Inputs

Low-Power, Low-Cost Transceiver Chipset


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Description

The MAX3890 serializer is ideal for converting 16-bit-wide, 155Mbps parallel data to 2.5Gbps serial data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock and data inputs for interfacing with high-speed digital circuitry, and delivers PECL serial data and clock outputs. A fully integrated PLL synthesizes an internal 2.5GHz serial clock from a 155.52MHz, 77.76MHz, 51.84MHz, or 38.88MHz reference clock. A loopback data output is provided to facilitate system diagnostic testing.

The MAX3890 is available in the extended temperature range (-40°C to +85°C) in a 64-pin TQFP exposed- paddle (EP) package.
MAX3890: Typical Operating Circuit MAX3890: Typical Operating Circuit Enlarge+

Key Features

  • Single +3.3V Supply
  • 495mW Power Consumption
  • Exceeds ANSI, ITU, and Bellcore Specifications
  • 155Mbps (16-bit wide) Parallel to 2.5Gbps Serial Conversion
  • Clock Synthesis for 2.5Gbps
  • Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz)
  • LVDS Parallel Clock and Data Inputs
  • Additional High-Speed Output for System Loopback Testing

Applications/Uses

  • 2.5Gbps ATM/SONET Access Nodes
  • 2.5Gbps SDH/SONET Transmission Systems
  • Add/Drop Multiplexers
  • ATM Backplanes
  • Digital Cross-Connects

Technical Documents

App Note 462 HFAN-04.0.2: Converting between RMS and Peak-to-Peak Jitter at a Specified BER

Quality and Environmental Data

Product Reliability Reports: MAX3890.pdf 
Lead-Free Package Tin (Sn) Whisker Reports

Tools & Models

  • MAX3890ECB IBIS Model
  • Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

    Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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