2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust
DescriptionThe MAX3877/MAX3878 are compact, low-power clock recovery and data retiming ICs for 2.488Gbps SONET/ SDH applications. The fully integrated phase-locked loop (PLL) recovers a synchronous clock signal from the serial NRZ data input, which is retimed by the recovered clock. An additional 2.488Gbps serial input is available for system loopback diagnostic testing, or this input can be connected to a 155MHz reference clock to maintain a valid clock output in the absence of data transitions. The MAX3877/MAX3878 provide vertical threshold and phase-adjust control to optimize system BER in DWDM applications.
These devices provide both loss-of-lock (active-low LOL) and loss-of-signal (LOS) monitors. Differential CML outputs are provided for both clock and data signals on the MAX3877, and differential PECL outputs are provided for clock and data signals on the MAX3878.
The MAX3877/MAX3878 are designed for both section-regenerator and terminal-receiver applications in OC-48/STM-16 transmission systems. Their jitter performance exceeds all of the SONET/SDH specifications. These devices operate from a single +3.0V to +3.6V supply over a -40°C to +85°C temperature range. Typical power consumption is only 540mW with a +3.3V supply (MAX3878). They are available in a 32-pin TQFP-EP package with an exposed pad, as well as in die form.
- Exceeds ANSI, ITU, and Bellcore SONET/SDH Specifications
- Adjustable Input Threshold (±180mV)
- 10mVp-p to 1.2Vp-p Differential Input Range
- 540mW Power Dissipation (at +3.3V)
- Fully Integrated Clock Recovery and Data Retiming
- Optional Holdover Capability (Using External Reference Clock)
- 0.003UIRMS Clock Jitter Generation
- Tolerates >2000 Consecutive Identical Digits
- Additional 2.488Gbps Input for Diagnostic Loopback Testing
- Differential PECL or CML Data and Clock Outputs
- Loss-of-Signal Indicator
- Loss-of-Lock Indicator
Technical DocumentsApp Note 987 HFAN-04.0.4: Jitter in Digital Communication Systems, Part 2
App Note 794 HFAN-04.0.3: Jitter in Digital Communication Systems, Part 1
App Note 462 HFAN-04.0.2: Converting between RMS and Peak-to-Peak Jitter at a Specified BER
|Device||Fab Process||Technology||Sample size||Rejects||FIT at 25°C||FIT at 55°C||Material Composition|
|App Note||987||HFAN-04.0.4: Jitter in Digital Communication Systems, Part 2|
|App Note||794||HFAN-04.0.3: Jitter in Digital Communication Systems, Part 1|
|App Note||462||HFAN-04.0.2: Converting between RMS and Peak-to-Peak Jitter at a Specified BER|