622Mbps, Low-Power, 3.3V Clock-Recovery and Data-Retiming IC with Limiting Amplifier

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The MAX3675 is a complete clock-recovery and data-retiming IC incorporating a limiting amplifier. It is intended for 622Mbps SDH/SONET applications and operates from a single +3.3V supply.

The MAX3675 has two differential input amplifiers: one accepts PECL levels, while the other accepts small-signal analog levels. The analog inputs access the limiting amplifier stage, which provides both a received-signal-strength indicator (RSSI) and a programmable-threshold loss-of-power (LOP) monitor. Selecting the PECL amplifier disables the limiting amplifier, conserving power. A loss-of-lock (LOL) monitor is also incorporated as part of the fully integrated PLL.
MAX3675: Typical Operating Circuit MAX3675: Typical Operating Circuit Enlarge+

Key Features

  • Single +3.3V or +5.0V Power Supply
  • Complies with ANSI, ITU, and Bellcore SDH/SONET Specifications
  • Low Power: 215mW at +3.3V
  • Selectable Data Inputs, Differential PECL or Analog
  • Received-Signal-Strength Indicator (RSSI)
  • Loss-of-Power and Loss-of-Lock Monitors
  • Differential PECL Clock and Data Outputs
  • No External Reference Clock Required


  • Add/Drop Multiplexers
  • ATM Switches
  • Digital Cross-Connects
  • SDH/SONET Access Nodes
  • SDH/SONET Transmission Systems
Request Reliability Report for: MAX3675 
Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C   Material Composition  

Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

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