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Quad IMUX Ethernet Mapper

Product Details

Key Features

Applications/Uses

Simplified Block Diagram

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Key Features

  • 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
  • Layer 1 Inverse Multiplexing Allows Bonding of Up to 4 T1/E1/J1 or DSL Links
  • Supports Up to 7.75ms Differential Delay
  • Channel (Byte) Interleaved Bus Operation
  • In-Band OAM and Signaling Capability
  • HDLC/LAPS Encapsulation with Programmable FCS, Interframe Fill
  • Committed Information Rate Controller Provides Fractional Allocation in 512kbps Increments
  • Programmable BERT for the Serial Interface
  • External 16MB, 100MHz SDRAM Buffering
  • Parallel Microprocessor Interface
  • 1.8V Operation with 3.3V Tolerant I/O
  • IEEE 1149.1 JTAG Support
  • Applications/Uses

    • Bonded Transparent LAN Service
    • Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
    • LAN Extension

    Description

    The DS33Z41 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over up to four interleaved PDH/TDM data streams using robust, balanced, and programmable inverse multiplexing. The Interleave Bus (IBO) serial link supports seamless bidirectional interconnection with Dallas Semiconductor's T1/E1 framers and transceivers.

    The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps.

    Simplified Block Diagram

    DS33Z41: Functional Diagram DS33Z41: Functional Diagram Zoom icon

    Technical Docs

    Support & Training

    Search our knowledge base for answers to your technical questions.

    Filtered Search

    Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .