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Ethernet Mapper

Product Details

Key Features

Simplified Block Diagram

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Key Features

  • 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
  • 52Mbps Synchronous TDM Serial Port with Independent Transmit and Receive Timing
  • HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
  • Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
  • Programmable BERT for Serial (TDM) Interface
  • External 16MB, 100MHz SDRAM Buffering
  • Parallel Microprocessor Interface
  • SPI Interface and Hardware Mode for Operation Without a Host Processor
  • Also Available in a 100-Ball, 10mm CSBGA— the Hardware/SPI Mode-Only DS33ZH11
  • 1.8V Operation with 3.3V Tolerant I/O
  • IEEE 1149.1 JTAG Support
  • Applications/Uses

    • Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
    • LAN Extension
    • Transparent LAN Service

    Description

    The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a PDH/TDM data stream. The serial link supports bidirectional-synchronous interconnect up to 52Mbps over xDSL, T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or SONET/SDH Tributary.

    The device performs store-and-forward of packets with full wire-speed transport capability. The built-in Committed Information Rate (CIR) controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33Z11 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode.

    Simplified Block Diagram

    DS33Z11: Functional Diagram DS33Z11: Functional Diagram Zoom icon

    Technical Docs

    Support & Training

    Search our knowledge base for answers to your technical questions.

    Filtered Search

    Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .