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DS3183

DS3183

Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU

Industry's First Multiport, T3/E3 ATM/Packet PHYs with Built-In Line Interface Units

Data Sheet
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Overview

Description

The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed, E3-framed, or clear-channel data streams on per-port basis.
DS3181, DS3182, DS3183, DS3184: Functional Diagram DS3181, DS3182, DS3183, DS3184: Functional Diagram Enlarge+

Key Features

  • Single (DS3181), Dual (DS3182), Triple (DS3183), or Quad (DS3184) with Integrated LIUATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52)
  • Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform
  • Each Port Independently Configurable
  • Perform Receive Clock/Data Recovery and Transmit Waveshaping
  • Jitter Attenuator can be Placed Either in the Receive or Transmit Paths
  • Interfaces to 75Ω Coaxial Cable at Lengths Up 380 Meters or 1246 Feet (DS3) or 440 Meters or 1443 Feet (E3)
  • Uses 1:2 Transformers on Both Tx and Rx
  • Universal PHYs Map ATM Cells and/or HDLC Packets into DS3 or E3 Data Streams
  • UTOPIA L2/L3 or POS-PHY™ L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width
  • 66MHz UTOPIA L3 and POS-PHY L3 Clock
  • 52MHz UTOPIA L2 and POS-PHY L2 Clock
  • Ports Independently Configurable for Cell or Packet Traffic in POS-PHY Bus Modes
  • Direct, PLCP, DSS, and Clear-Channel Cell Mapping

Applications/Uses

  • Access Concentrators
  • ATM and Frame Relay Equipment
  • Digital Cross Connect
  • Integrated Access Device (IAD)
  • Multiservice Access Platform (MSAP)
  • Multiservice Protocol Platform (MSPP)
  • PBXs
  • PDH Multiplexer/Demultiplexer
  • Routers and Switches
  • SONET/SDH ADM
  • SONET/SDH Muxes
  • Test Equipment

Design Resources

Technical Documents

App Note 3763 Measuring and Improving Return Loss on the DS317x and DS318x T3/E3/STS-1 LIUs
App Note 3670 Measuring Return Loss Using the Advantest R3132 Spectrum Analyzer
App Note 3609 Clock-Rate-Adapter (CLAD) Features for DS325X, DS316X, DS317X, and DS318X
App Note 3547 Measuring Return Loss on T3/E3/STS-1 LIUs
App Note 3410 Guidelines for Laying Out T3 and E3 Network Interfaces
App Note 3409 Configuration of CLAD for DS318x
App Note 351 T1/E1 and T3/E3 Transformer Selection Guide

Quality and Environmental Data

Product Reliability Reports: DS3183.pdf 
Lead-Free Package Tin (Sn) Whisker Reports

Tools & Models

  • DS3183 A2 BSDL Model
  • DS3183 IBIS Model

    • CAD Symbols and Footprints

  • DS3183
  • DS3183N
    •

    Quality And Environmental

    Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

    Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

    Quality Management System >
    Environmental Management System >

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    Reference Designs

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    Events


    Electronics in Vehicles (ELIV) 2019
    10/16/2019 - 10/17/2019, Bonn, Germany
    The international VDI Congress ELIV (Electronics In Vehicles) is THE event for all experts in the field of electrical and electronical car engineering and integration of mechanical and electronical systems.

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