DS26522
Dual T1/E1/J1 Transceiver
Dual Transceiver Saves Board Space and Power
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Key Features
Applications/Uses
Simplified Block Diagram
Technical Docs
| Data Sheet | Dual T1/E1/J1 Transceiver | Nov 12, 2009 | |
| App Note | How to Transmit/Receive SSMs in the DS26521 and DS2155 | ||
| App Note | Handling Performance Report Messages in the DS2155 | ||
| App Note | Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation | ||
| App Note | DS26522 JTAG Scan Chain Mapping | ||
| App Note | T1/E1 and T3/E3 Transformer Selection Guide | ||
| App Note | Interfacing to the Fractional T1 and E1 | ||
| App Note | Legacy T1/E1 8MHz Backplane Operation | ||
| App Note | How to Use the Bit-Error-Rate Tester (BERT) on the DS2652x STCs |
Support & Training
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Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
Key Features
- Complete T1, E1, or J1 Long-Haul/Short-Haul Transceiver (LIU plus Framer)
- Internal Software-Selectable Transmit- and Receive-Side Termination for 100Ω T1 Twisted Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair, and 75Ω E1 Coaxial Applications
- Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path; Jitter Attenuator Meets ETS CTR 12/13, ITU-T G.736, G.742, G.823, and AT&T Pub 62411
- External Master Clock can be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 Operation; This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode
- Receive-Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments
- Transmit Open- and Short-Circuit Detection
- LIU LOS in Accordance with G.775, ETS 300 233, and T1.231
- Transmit Synchronizer
- Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port
- Alarm Detection and Insertion
- T1 Framing Formats of D4, SLC-96, and ESF
- J1 Support
- E1 G.704 and CRC-4 Multiframe
- Controlled by 8-Bit Parallel Port Interface or Serial Peripheral Interface (SPI)
Applications/Uses
- Channel Banks
- Channel Service Units (CSUs)
- Data Service Units (DSUs)
- Muxes
- Routers
- Switches
- T1/E1 Test Equipment
Description
Technical Docs
| Data Sheet | Dual T1/E1/J1 Transceiver | Nov 12, 2009 | |
| App Note | How to Transmit/Receive SSMs in the DS26521 and DS2155 | ||
| App Note | Handling Performance Report Messages in the DS2155 | ||
| App Note | Tech Brief 7: DS2152 and DS2154 8MHz System Clock Operation | ||
| App Note | DS26522 JTAG Scan Chain Mapping | ||
| App Note | T1/E1 and T3/E3 Transformer Selection Guide | ||
| App Note | Interfacing to the Fractional T1 and E1 | ||
| App Note | Legacy T1/E1 8MHz Backplane Operation | ||
| App Note | How to Use the Bit-Error-Rate Tester (BERT) on the DS2652x STCs |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .
Sampling:
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
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