16-Port Transmission Convergence Device

Please check latest availability status for a specific part variant.


On the transmit side, the DS26102 receives ATM cells from an ATM device through a UTOPIA II interface, provides cell buffering (up to 4 cells), HEC generation and insertion, cell scrambling, and converts the data to a serial stream appropriate for interfacing to a T1/E1 framer or transceiver. On the receive side, the DS26102 receives a TDM stream from a T1/E1 framer or transceiver; searches for the cell alignment; verifies the HEC; provides cell filtering, descrambling, and cell buffering; and passes the cells to an ATM device through the UTOPIA II interface. Other low-level traffic management functions are selectable for the transmit and receive paths. The DS26102 can also be used in fractional T1/E1 applications.

The DS26102 maps ATM cells to T1/E1 TDM frames as per the ATM Forum Specifications af-phy-0016.000 and af-phy-0064.000. In the receive direction, the cell delineation mechanism used for finding ATM cell boundary within T1/E1 frame is performed as per ITU I.432. The DS26102 provides a mapping solution for up to 16 T1/E1 TDM ports. The terms physical layer (PHY) and line side are used synonymously in this document and refer to the device interfacing with the line side of the DS26102. The terms ATM layer and system side are used synonymously and refer to the DS26102's UTOPIA II interface.

Key Features

  • Supports 16 T1/E1 TDM Ports
  • Supports Fractional T1/E1
  • Compliant to ATM Forum Specifications for ATM Over T1 and E1
  • Standard UTOPIA II Interface to the ATM Layer
  • Configurable UTOPIA Address Range
  • Configurable Tx FIFO Depth to 2, 3, or 4 Cells
  • Optional Payload Scrambling in Transmit Direction and Descrambling in Receive Direction per ITU I.432
  • Optional HEC Insertion in Transmit Direction with Programmable COSET Polynomial Addition
  • HEC-Based Cell Delineation
  • Single-Bit HEC Error Correction in the Receive Direction
  • Receive HEC-Errored Cell Filtering
  • Receive Idle/Unassigned Cell Filtering
  • User-Definable Cell Filtering
  • 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor Interface
  • Internal Clock Generator Eliminates External High-Speed Clocks
  • Internal One-Second Timer
  • Detects/Reports Up to Eight External Status Signals with Interrupt Support
  • IEEE 1149.1 JTAG Boundary Scan Support
  • 17mm x 17mm, 256-Pin CSBGA


  • ATM Over T1/E1
  • DSLAMs
  • IMA
  • Routers/Switches

Quality and Environmental Data

Product Reliability Reports: DS26102.pdf 
Lead-Free Package Tin (Sn) Whisker Reports

Tools & Models

  • DS26102 BSDL Model
  • Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

    Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

    Quality Management System >
    Environmental Management System >


    Related Resources

    16-Bit, 5.9Gsps Interpolating and Modulating RF DAC with JESD204B Interface

    • Simplifies RF Design and Enables New Wireless Communication Architectures
    • Direct RF Synthesis of 600MHz Bandwidth Up to 2.8GHz
    • Highly Flexible and Configurable

    Electronics in Vehicles (ELIV) 2019
    10/16/2019 - 10/17/2019, Bonn, Germany
    The international VDI Congress ELIV (Electronics In Vehicles) is THE event for all experts in the field of electrical and electronical car engineering and integration of mechanical and electronical systems.