DS21552

3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers


Please check latest availability status for a specific part variant.

Description

The DS21352/552 T1 single chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX-1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX-1 line build outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
DS21352, DS21552: Pin Assignment DS21352, DS21552: Pin Assignment Enlarge+

Key Features

  • Complete DS1/ISDN-PRI/J1 transceiver functionality
  • Long and Short haul LIU
  • Crystal-less jitter attenuator
  • Generates DSX-1 and CSU line build-outs
  • HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation
  • Dual two-frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz
  • 8.192MHz clock output locked to RCLK
  • Interleaving PCM Bus Operation
  • Per-channel loopback and idle code insertion
  • 8-bit parallel control port muxed or nonmuxed buses (Intel or Motorola)
  • Programmable output clocks for Fractional T1
  • Fully independent transmit and receive functionality
  • Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes
  • IEEE 1149.1 JTAG-Boundary Scan
  • Pin compatible with DS2152/54/354/554 SCTs
  • 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply; low power CMOS

Technical Documents

App Note 3760 Interleaved Bus Operation
App Note 3547 Measuring Return Loss on T3/E3/STS-1 LIUs
App Note 3349 T1/E1 Loopback Operation for Maxim T1/E1/J1 Transceivers
App Note 3208 Elastic Store Operation
App Note 3121 Selecting a T1/E1/J1 Single-Chip Transceiver
App Note 2713 Switching Frame Mode In Live T1 Systems
App Note 461 Programming and Controlling the FDL on DS2141A, DS2151
App Note 405 Power-Fault Protection Layout
App Note 394 HDLC Configuration of Framers and Transceivers
App Note 391 NRZ Applications
App Note 388 Hitless Protection Switching with 1+1 Redundancy
App Note 382 J1 Japanese Standards
App Note 379 Conversion Between T1 and E1
App Note 374 DS2155 vs. DS21x5y: Software and Hardware Considerations
App Note 370 Using RCLK in a BITS/SSU Application
App Note 360 DS21352/DS21552 versus DS2152 Single Chip Transceiver
App Note 355 DS21Q4x, DS215x, and DS21x5y Test Registers
App Note 351 T1/E1 and T3/E3 Transformer Selection Guide
App Note 345 DS21352/552, DS2151, DS2152, DS2141A, DS21Q42 Programming SLC-96
App Note 342 T1/E1 Framer Initialization and Programming
App Note 337 DS2151 Implementation of ANSI T1.231-1993
App Note 336 Transparent Operation on T1, E1 Framers and Transceivers
App Note 325 DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide
App Note 324 T1/E1 Network Interface Design
App Note 319 DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32)
App Note 310 D4 Framing and Signaling
App Note 309 Interfacing to the Fractional T1 and E1
App Note 307 DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert

Quality and Environmental Data

Product Reliability Reports: DS21552.pdf 
Lead-Free Package Tin (Sn) Whisker Reports

Additional Resources

Development Kit

Tools & Models

  • DS21552 BSDL Model
  • CAD Symbols and Footprints

  • DS21552L+
  • DS21552LN+
  • Device   Fab Process   Technology   Sample size   Rejects   FIT at 25°C   FIT at 55°C  

    Note : The failure rates are summarized by technology and mapped to the associated material part numbers. The failure rates are highly dependent on the number of units tested.

    Quality Management System >
    Environmental Management System >

     
    Status:
    Package:
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    Related Resources

    Type ID PDF Title
    App Note 3760 Interleaved Bus Operation
    App Note 3547 Measuring Return Loss on T3/E3/STS-1 LIUs
    App Note 3349 T1/E1 Loopback Operation for Maxim T1/E1/J1 Transceivers
    App Note 3208 Elastic Store Operation
    App Note 3121 Selecting a T1/E1/J1 Single-Chip Transceiver
    App Note 2713 Switching Frame Mode In Live T1 Systems
    App Note 461 Programming and Controlling the FDL on DS2141A, DS2151
    App Note 405 Power-Fault Protection Layout
    App Note 394 HDLC Configuration of Framers and Transceivers
    App Note 391 NRZ Applications
    App Note 388 Hitless Protection Switching with 1+1 Redundancy
    App Note 382 J1 Japanese Standards
    App Note 379 Conversion Between T1 and E1
    App Note 374 DS2155 vs. DS21x5y: Software and Hardware Considerations
    App Note 370 Using RCLK in a BITS/SSU Application
    App Note 360 DS21352/DS21552 versus DS2152 Single Chip Transceiver
    App Note 355 DS21Q4x, DS215x, and DS21x5y Test Registers
    App Note 351 T1/E1 and T3/E3 Transformer Selection Guide
    App Note 345 DS21352/552, DS2151, DS2152, DS2141A, DS21Q42 Programming SLC-96
    App Note 342 T1/E1 Framer Initialization and Programming
    App Note 337 DS2151 Implementation of ANSI T1.231-1993
    App Note 336 Transparent Operation on T1, E1 Framers and Transceivers
    App Note 325 DS2151, DS2152, DS2153, DS2154 Dallas Single Chip Transceiver Crystal Selection Guide
    App Note 324 T1/E1 Network Interface Design
    App Note 319 DS2152, DS2154, DS21x5Y, and DS2155 Interfacing to the MC68360 (QUICC32)
    App Note 310 D4 Framing and Signaling
    App Note 309 Interfacing to the Fractional T1 and E1
    App Note 307 DS2152, DS2154, DS2151, DS2153, DS21X5Y and DS2155 Three Channel Drop and Insert

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