Product Details
Key Features
Applications/Uses
Simplified Block Diagram
Technical Docs
Data Sheet | Octal, 14-Bit Voltage-Output DAC with Parallel Interface | Aug 14, 2003 |
Support & Training
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Key Features
- Full 14-Bit Performance Without Adjustments
- Eight DACs in a Single Package
- Buffered Voltage Outputs
- Unipolar or Bipolar Voltage Swing of (VSS + 2.5V) to (VDD - 2.5V)
- 31µs Output Settling Time
- Low Power Consumption: 8mA (typ)
- Small 44-Pin MQFP Package
- Double-Buffered Digital Inputs
- Asynchronous Load Updates All DACs Simultaneously
- Asynchronous Active-Low CLR Forces All DACs to DUTGND_ _ Potential
Applications/Uses
- Arbitrary Function Generators
- Automated Test Equipment (ATE)
- Avionics Equipment
- Digital Offset and Gain Adjustments
- Industrial Process Controls
- Minimum Component Count Analog Systems
- SONET Applications
Description
The MX7841 features double-buffered interface logic with a 14-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (active-low LDAC) transfers data from the input latch to the DAC latch. The active-low LDAC input controls all DACs; therefore, all DACs can be updated simultaneously by asserting active-low LDAC. An asynchronous active-low CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that active-low CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The MX7841 is pin-for-pin compatible with AD7841.
Technical Docs
Data Sheet | Octal, 14-Bit Voltage-Output DAC with Parallel Interface | Aug 14, 2003 |
Support & Training
Search our knowledge base for answers to your technical questions.
Filtered SearchOur dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .