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14-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs

Product Details

Key Features

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 14
# Channels 2
fCLK (Msps) 250
SFDR (dBc) (@ fOUT) 75 @ 16MHz
DNL (±LSB) 0.2
INL (±LSB) 0.5
IOUT (mA) 20
PDISS (mW) 287
Interface Parallel, LVDS
VSUPPLY (V) 3.3
Package/Pins QFN/68
Budgetary
Price (See Notes)
18.04
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Simplified Block Diagram

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Parameters

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 14
# Channels 2
fCLK (Msps) 250
SFDR (dBc) (@ fOUT) 75 @ 16MHz
DNL (±LSB) 0.2
INL (±LSB) 0.5
IOUT (mA) 20
PDISS (mW) 287
Interface Parallel, LVDS
VSUPPLY (V) 3.3
Package/Pins QFN/68
Budgetary
Price (See Notes)
18.04

Key Features

  • 250Msps Output Update Rate
  • Noise Spectral Density = -160dBFS/Hz at fOUT = 16MHz
  • Excellent SFDR and IMD Performance
    • SFDR = 75dBc at fOUT = 16MHz (to Nyquist)
    • SFDR = 71dBc at fOUT = 80MHz (to Nyquist)
    • IMD = -87dBc at fOUT = 10MHz
    • IMD = -73dBc at fOUT = 80MHz
  • ACLR = 75dB at fOUT = 61MHz
  • 2mA to 20mA Full-Scale Output Current
  • LVDS-Compatible Digital and Clock Inputs
  • On-Chip +1.20V Bandgap Reference
  • Low 287mW Power Dissipation
  • Compact 68-Pin QFN-EP Package (10mm x 10mm)
  • Evaluation Kit Available (MAX5878EVKIT)

Applications/Uses

  • Automated Test Equipment (ATE)
  • Base Stations: Single-/Multicarrier UMTS, CDMA, GSM
  • Cable Modem Termination Systems (CMTS)
  • Communications: Fixed Broadband Wireless Access, Point-to-Point Microwave
  • Direct Digital Synthesis (DDS)
  • Instrumentation

Description

The MAX5877 is an advanced 14-bit, 250Msps, dual digital-to-analog converter (DAC). This DAC meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. Operating from +3.3V and +1.8V supplies, this dual DAC offers exceptional dynamic performance such as 75dBc spurious-free dynamic range (SFDR) at fOUT = 16MHz and supports update rates of 250Msps, with a power dissipation of only 287mW.

The MAX5877 utilizes a current-steering architecture that supports a 2mA to 20mA full-scale output current range, and allows a 0.1VP-P to 1VP-P differential output voltage swing. The device features an integrated +1.2V bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. A separate reference input (REFIO) allows for the use of an external reference source for optimum flexibility and improved gain accuracy.

The clock inputs of the MAX5877 accept both LVDS and LVPECL-compatible voltage levels. The device features an interleaved data input that allows a single LVDS bus to support both DACs. The MAX5877 is available in a 68-pin QFN package with an exposed pad (EP) and is specified for the extended temperature range (-40°C to +85°C).

Refer to the MAX5876 and MAX5878 data sheets for pin-compatible 12-bit and 16-bit versions of the MAX5877, respectively. Refer to the MAX5874 data sheet for a CMOS-compatible version of the MAX5877.

See a parametric table of the complete family of pin-compatible 12-/14-/16-bit high-speed DACs.

Simplified Block Diagram

MAX5877: Pin Configuration MAX5877: Pin Configuration Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .