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Dual 8-Bit, 300Msps DAC with 4x/2x/1x Interpolation Filters and PLL

Product Details

Key Features

Simplified Block Diagram

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Key Features

  • 8-Bit Resolution, Dual DAC
  • 300Msps Update Rate
  • Integrated 4x/2x/1x Interpolating Filters
  • Internal PLL Multiplier
  • 2.7V to 3.3V Single Supply
  • Full Output Swing and Dynamic Performance at 2.7V Supply
  • Superior Dynamic Performance: 68dBc SFDR at fOUT = 20MHz
  • Programmable Channel Gain Matching
  • Integrated 1.24V Low-Noise Bandgap Reference
  • Single-Resistor Gain Control
  • Interleave Data Mode
  • Differential Clock Input Modes
  • EV Kit Available—MAX5858AEVKIT

Applications/Uses

  • Communications
  • Direct Digital Synthesis (DDS)
  • Instrumentation/ATE
  • Point-to-Point Microwave Links
  • SatCom, LMDS, MMDS, HFC, DSL, WLAN,
  • Wireless Base Stations

Description

The MAX5856A dual, 8-bit, 300Msps digital-to-analog converter (DAC) provides superior dynamic performance in wideband communication systems. The MAX5856A integrates two 8-bit DAC cores, 4x/2x/1x programmable digital interpolation filters, phase-lock loop (PLL) clock multiplier, and a 1.24V reference. The MAX5856A supports single-ended and differential modes of operation. The MAX5856A dynamic performance is maintained over the entire power-supply operating range of 2.7V to 3.3V. The analog outputs support a compliance voltage of -1.0V to +1.25V.

The 4x/2x/1x programmable interpolation filters feature excellent passband distortion and noise performance. Interpolating filters minimize the design complexity of analog reconstruction filters while lowering the data bus and the clock speeds of the digital interface. The PLL multiplier generates all internal synchronized high-speed clock signals for interpolating filter operation and DAC core conversion. The internal PLL helps minimize system complexity and lower cost. To reduce the I/O pin count, the DAC can also operate in interleave data mode. This allows the MAX5856A to be updated on a single 8-bit bus.

The MAX5856A features digital control of channel gain matching to within ±0.4dB in sixteen 0.05dB steps. Channel matching improves sideband suppression in analog quadrature modulation applications. The on-chip 1.24V bandgap reference includes a control amplifier that allows external full-scale adjustments of both channels through a single resistor. The internal reference can be disabled and an external reference may be applied for high-accuracy applications.

The MAX5856A features full-scale current outputs of 2mA to 20mA and operates from a 2.7V to 3.3V single supply. The DAC supports three modes of power-control operation: normal, low-power standby, and complete power-down. In power-down mode, the operating current is reduced to 1µA.

The MAX5856A is packaged in a 48-pin TQFP with exposed paddle (EP) for enhanced thermal dissipation and is specified for the extended (-40°C to +85°C) operating temperature range.

Simplified Block Diagram

MAX5856A: Typical Application Circuit MAX5856A: Typical Application Circuit Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .