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14-Bit 3.072Gsps RF DAC

RF DAC Enables Fully Digital Upconverter for DOCSIS 3.1 Remote PHY Devices and CCAP

Product Details

Key Features

Applications/Uses

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 14
# Channels 1
fCLK (Msps) 3072
SFDR (dBc) (@ fOUT) 74 @ 1000MHz
DNL (±LSB) 1.5
INL (±LSB) 3
IOUT (mA) 40
PDISS (mW) 2400
Interface JESD204B
VSUPPLY (V) 1
Package/Pins FCBGA/144
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Parameters

Parametric specs for High-Speed DACs (≥ 1MHz)
Resolution (bits) 14
# Channels 1
fCLK (Msps) 3072
SFDR (dBc) (@ fOUT) 74 @ 1000MHz
DNL (±LSB) 1.5
INL (±LSB) 3
IOUT (mA) 40
PDISS (mW) 2400
Interface JESD204B
VSUPPLY (V) 1
Package/Pins FCBGA/144

Key Features

  • Simplifies RF Design and Enables New Communication Architectures
    • Enables Multi-Band RF Modulation
  • Direct RF Synthesis of 1.5GHz Bandwidth
    • 3.072Gsps DAC Output Update Rate
    • High-Performance 14-Bit RF DAC Core
  • Highly Flexible and Configurable
    • 6-Lane JESD204B Input Data Interface
    • 10.24Gbps Serial Data Rate
    • Subclass-0 Compliant
    • Divided Reference Clock Output
    • SPI Interface for Device Configuration

Applications/Uses

  • Cable Modem Termination Systems (CMTS)
  • Digital Video Broadcast Modulators
  • DOCSIS 3.1 Remote PHY Devices, CCAP
  • Edge QAM Devices
  • Ethernet PON over Coax (EPoC)
  • Instrumentation

Description

The MAX5850 is a 14-Bit, 3.072Gsps digital-to-analog converter (DAC) and can directly synthesize 1.5GHz of instantaneous bandwidth in baseband. The device is optimized for cable access and digital video broadcast applications and meets spectral emission requirements for a broad set of radio transmitters and modulators, including DOCSIS 3.1/3.0, DVB-C/-C2, DVB-T2, ISDB-T, and EPoC.

The MAX5850 accepts input data through a six-lane JESD204B serializer/deserializer (SerDes) interface at 10.24Gbps that is Subclass-0 compliant. The MAX5850 clock input has a flexible clock interface that accepts a differential sine or square-wave input clock signal at frequencies equal to the DAC update rate of 3.072GHz. The device outputs a divided reference clock to ensure synchronization of the system clock and DAC clock.

The integrated RF DAC uses a differential current-steering architecture that includes a differential 50Ω internal termination and can produce a 2.5dBm full-scale output signal level on a 50Ω external load. Operating from 1.8V and 1.0V power supplies, the device consumes 2.4W at 3.072Gsps. The device is offered in a compact 144-pin, 10mm x 10mm, FCCSP package and is specified for the extended industrial temperature range (-40°C to +85°C).

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .