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Ultra-Small, Octal Channel, 8-/10-/12-Bit Buffered Output DACs with Internal Reference and I2C Interface

Feature-Rich, 8-Channel DAC Family Offered in a 5.75mm2 WLP Footprint

Product Details

Key Features

Applications/Uses

Simplified Block Diagram

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Key Features

  • Eight High-Accuracy DAC Channels
    • 12-Bit Accuracy Without Adjustment
    • ±1 LSB INL Buffered Voltage Output
    • Guaranteed Monotonic Over All Operating Conditions
    • Independent Mode Settings for Each DAC
  • Three Precision Selectable Internal References
    • 2.048V, 2.500V, or 4.096V
  • Internal Output Buffer
    • Rail-to-Rail Operation with External Reference
    • 4.5µs Settling Time
    • Outputs Directly Drive 2kΩ Loads
  • Small 6.5mm × 4.4mm 20-Pin TSSOP or Ultra-Small 2.5mm × 2.3mm 20-Bump WLP Package
  • Wide 2.7V to 5.5V Supply Range
  • Separate 1.8V to 5.5V VDDIO Power-Supply Input
  • Fast 400kHz I2C-Compatible, 2-Wire Serial Interface
  • Pin-Selectable Power-On-Reset to Zero-Scale or Midscale DAC Output
  • Active-Low LDAC and Active-Low CLR For Asynchronous DAC Control
  • Three Software-Selectable Power-Down Output Impedances
    • 1kΩ, 100kΩ, or High Impedance

Applications/Uses

  • Automatic Tuning and Optical Control
  • Gain and Offset Adjustment
  • Portable Instrumentation
  • Power Amplifier Control and Biasing
  • Process Control and Servo Loops
  • Programmable Voltage and Current Sources

Description

The MAX5823/MAX5824/MAX5825 8-channel, low-power, 8-/10-/12-bit, voltage-output digital-to-analog converters (DACs) include output buffers and an internal 3ppm/°C reference that is selectable to be 2.048V, 2.500V, or 4.096V. The MAX5823/MAX5824/MAX5825 accept a wide supply voltage range of 2.7V to 5.5V with extremely low power (6mW) consumption to accommodate most low-voltage applications. A precision external reference input allows rail-to-rail operation and presents a 100kΩ (typ) load to an external reference.

The MAX5823/MAX5824/MAX5825 have an I2C-compatible, 2-wire interface that operates at clock rates up to 400kHz. The DAC output is buffered and has a low supply current of less than 250µA per channel and a low offset error of ±0.5mV (typ). On power-up, the MAX5823/ MAX5824/MAX5825 reset the DAC outputs to zero or midscale based on the status of M/active-low Z logic input, providing flexibility for a variety of control applications. The internal reference is initially powered down to allow use of an external reference. The MAX5823/MAX5824/MAX5825 allow simultaneous output updates using software LOAD commands or the hardware load DAC logic input (active-low LDAC).

The MAX5823/MAX5824/MAX5825 feature a watchdog function which can be enabled to monitor the I/O interface for activity and integrity.

A clear logic input (active-low CLR) allows the contents of the CODE and the DAC registers to be cleared asynchronously and simultaneously sets the DAC outputs to the programmable default value. The MAX5823/MAX5824/MAX5825 are available in a 20-pin TSSOP and an ultra-small, 20-bump WLP package and are specified over the -40°C to +125°C temperature range.

Simplified Block Diagram

MAX5823, MAX5824, MAX5825: Functional Diagram MAX5823, MAX5824, MAX5825: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .