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2.7V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers

Smallest Quad 8-Bit DAC

Product Details

Key Features

Parametric specs for Precision DACs (< 1MHz)
Resolution (bits) 8
# Channels 4
Interface Serial - SPI
Output Type Voltage- Buffered
Reference Ext.
INL (±LSB) (max) 1
2
Supply Range (V) (min) 2.7
Supply Range (V) (max) 3.6
ICC (mA) (max) 1.5
Settling Time (µs) (typ) 6
Package/Pins QSOP/16
Oper. Temp. (°C) -55 to +125
-40 to +85
0 to +70
Budgetary
Price (See Notes)
3.28
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Simplified Block Diagram

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Parameters

Parametric specs for Precision DACs (&lt; 1MHz)
Resolution (bits) 8
# Channels 4
Interface Serial - SPI
Output Type Voltage- Buffered
Reference Ext.
INL (±LSB) (max) 1
2
Supply Range (V) (min) 2.7
Supply Range (V) (max) 3.6
ICC (mA) (max) 1.5
Settling Time (µs) (typ) 6
Package/Pins QSOP/16
Oper. Temp. (°C) -55 to +125
-40 to +85
0 to +70
Budgetary
Price (See Notes)
3.28

Key Features

  • +2.7V to +3.6V Single-Supply Operation
  • Ultra-Low Supply Current:
    • 0.7mA while Operating
    • 1µA in Shutdown Mode
  • Ultra-Small 16-Pin QSOP Package
  • Ground to VDD Reference Input Range
  • Output Buffer Amplifiers Swing Rail to Rail
  • 10MHz Serial Interface, Compatible with SPI, QSPI
    • (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire
  • Double-Buffered Registers for Synchronous Updating
  • Serial Data Output for Daisy Chaining
  • Power-On Reset Clears Serial Interface and Sets All Registers to Zero
  • Software Shutdown
  • Software-Programmable Logic Output
  • Asynchronous Hardware Clear Resets All Internal Registers to Zero

Applications/Uses

  • Digital Gain and Offset Control
  • Portable Instrumentation
  • Programmable Attenuators
  • Programmable Current Sources

Description

The MAX533 serial-input, voltage-output, 8-bit quad digital-to-analog converter (DAC) operates from a sin-gle +2.7V to +3.6V supply. Internal precision buffers swing rail to rail, and the reference input range includes both ground and the positive rail. The MAX533 features a 1µA shutdown mode.

The serial interface is double buffered: a 12-bit input shift register is followed by four 8-bit buffer registers and four 8-bit DAC registers. The 12-bit serial word consists of eight data bits and four control bits (for DAC selection and special programming commands). Both the input and DAC registers can be updated indepen-dently or simultaneously with a single software com-mand. Two additional asynchronous control pins, active-low LDAC and active-low CLR, provide simultaneous updating or clearing of the input and DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL = CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A buffered data output allows daisy chaining of serial devices.

In addition to 16-pin DIP and CERDIP packages, the MAX533 is available in a 16-pin QSOP that occupies the same area as an 8-pin SO.

Simplified Block Diagram

MAX533: Functional Diagram MAX533: Functional Diagram Zoom icon

Technical Docs

Support & Training

Search our knowledge base for answers to your technical questions.

Filtered Search

Our dedicated team of Applications Engineers are also available to answer your technical questions. Visit our support portal .